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R600: Emit CF_ALU and use true kcache register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178503 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune
parent
19801a6481
commit
8e59191eb8
@ -23,6 +23,7 @@ class AMDGPUTargetMachine;
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// R600 Passes
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FunctionPass* createR600KernelParametersPass(const DataLayout *TD);
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FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
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FunctionPass *createR600EmitClauseMarkers(TargetMachine &tm);
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// SI Passes
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FunctionPass *createSIAnnotateControlFlowPass();
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@ -151,6 +151,7 @@ bool AMDGPUPassConfig::addPreEmitPass() {
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if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
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addPass(createAMDGPUCFGPreparationPass(*TM));
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addPass(createAMDGPUCFGStructurizerPass(*TM));
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addPass(createR600EmitClauseMarkers(*TM));
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addPass(createR600ExpandSpecialInstrsPass(*TM));
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addPass(&FinalizeMachineBundlesID);
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} else {
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@ -101,7 +101,8 @@ enum InstrTypes {
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INSTR_FC,
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INSTR_NATIVE,
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INSTR_VTX,
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INSTR_EXPORT
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INSTR_EXPORT,
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INSTR_CFALU
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};
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enum FCInstr {
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@ -251,6 +252,13 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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Emit(Inst, OS);
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break;
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}
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case AMDGPU::CF_ALU:
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case AMDGPU::CF_ALU_PUSH_BEFORE: {
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uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
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EmitByte(INSTR_CFALU, OS);
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Emit(Inst, OS);
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break;
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}
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default:
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EmitALUInstr(MI, Fixups, OS);
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253
lib/Target/R600/R600EmitClauseMarkers.cpp
Normal file
253
lib/Target/R600/R600EmitClauseMarkers.cpp
Normal file
@ -0,0 +1,253 @@
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//===-- R600EmitClauseMarkers.cpp - Emit CF_ALU ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Add CF_ALU. R600 Alu instructions are grouped in clause which can hold
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/// 128 Alu instructions ; these instructions can access up to 4 prefetched
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/// 4 lines of 16 registers from constant buffers. Such ALU clauses are
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/// initiated by CF_ALU instructions.
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "R600RegisterInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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namespace llvm {
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class R600EmitClauseMarkersPass : public MachineFunctionPass {
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private:
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static char ID;
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const R600InstrInfo *TII;
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unsigned OccupiedDwords(MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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case AMDGPU::INTERP_PAIR_XY:
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case AMDGPU::INTERP_PAIR_ZW:
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case AMDGPU::INTERP_VEC_LOAD:
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case AMDGPU::DOT4_eg_pseudo:
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case AMDGPU::DOT4_r600_pseudo:
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return 4;
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case AMDGPU::KILL:
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return 0;
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default:
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break;
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}
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if(TII->isVector(*MI) ||
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TII->isCubeOp(MI->getOpcode()) ||
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TII->isReductionOp(MI->getOpcode()))
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return 4;
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unsigned NumLiteral = 0;
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for (MachineInstr::mop_iterator It = MI->operands_begin(),
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E = MI->operands_end(); It != E; ++It) {
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MachineOperand &MO = *It;
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if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
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++NumLiteral;
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}
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return 1 + NumLiteral;
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}
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bool isALU(const MachineInstr *MI) const {
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if (MI->getOpcode() == AMDGPU::KILLGT)
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return false;
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if (TII->isALUInstr(MI->getOpcode()))
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return true;
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if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
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return true;
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switch (MI->getOpcode()) {
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case AMDGPU::PRED_X:
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case AMDGPU::INTERP_PAIR_XY:
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case AMDGPU::INTERP_PAIR_ZW:
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case AMDGPU::INTERP_VEC_LOAD:
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case AMDGPU::COPY:
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case AMDGPU::DOT4_eg_pseudo:
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case AMDGPU::DOT4_r600_pseudo:
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return true;
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default:
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return false;
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}
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}
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bool IsTrivialInst(MachineInstr *MI) const {
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switch (MI->getOpcode()) {
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case AMDGPU::KILL:
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case AMDGPU::RETURN:
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return true;
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default:
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return false;
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}
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}
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// Register Idx, then Const value
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std::vector<std::pair<unsigned, unsigned> > ExtractConstRead(MachineInstr *MI)
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const {
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const R600Operands::Ops OpTable[3][2] = {
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{R600Operands::SRC0, R600Operands::SRC0_SEL},
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{R600Operands::SRC1, R600Operands::SRC1_SEL},
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{R600Operands::SRC2, R600Operands::SRC2_SEL},
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};
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std::vector<std::pair<unsigned, unsigned> > Result;
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if (!TII->isALUInstr(MI->getOpcode()))
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return Result;
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for (unsigned j = 0; j < 3; j++) {
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int SrcIdx = TII->getOperandIdx(MI->getOpcode(), OpTable[j][0]);
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if (SrcIdx < 0)
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break;
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if (MI->getOperand(SrcIdx).getReg() == AMDGPU::ALU_CONST) {
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unsigned Const = MI->getOperand(
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TII->getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
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Result.push_back(std::pair<unsigned, unsigned>(SrcIdx, Const));
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}
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}
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return Result;
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}
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std::pair<unsigned, unsigned> getAccessedBankLine(unsigned Sel) const {
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// Sel is (512 + (kc_bank << 12) + ConstIndex) << 2
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// (See also R600ISelLowering.cpp)
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// ConstIndex value is in [0, 4095];
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return std::pair<unsigned, unsigned>(
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((Sel >> 2) - 512) >> 12, // KC_BANK
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// Line Number of ConstIndex
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// A line contains 16 constant registers however KCX bank can lock
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// two line at the same time ; thus we want to get an even line number.
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// Line number can be retrieved with (>>4), using (>>5) <<1 generates
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// an even number.
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((((Sel >> 2) - 512) & 4095) >> 5) << 1);
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}
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bool SubstituteKCacheBank(MachineInstr *MI,
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std::vector<std::pair<unsigned, unsigned> > &CachedConsts) const {
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std::vector<std::pair<unsigned, unsigned> > UsedKCache;
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std::vector<std::pair<unsigned, unsigned> > Consts = ExtractConstRead(MI);
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assert(TII->isALUInstr(MI->getOpcode()) && "Can't assign Const");
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for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
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unsigned Sel = Consts[i].second;
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unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
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unsigned KCacheIndex = Index * 4 + Chan;
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const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
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if (CachedConsts.empty()) {
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CachedConsts.push_back(BankLine);
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UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
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continue;
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}
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if (CachedConsts[0] == BankLine) {
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UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
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continue;
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}
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if (CachedConsts.size() == 1) {
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CachedConsts.push_back(BankLine);
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UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
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continue;
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}
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if (CachedConsts[1] == BankLine) {
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UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
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continue;
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}
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return false;
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}
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for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
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switch(UsedKCache[i].first) {
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case 0:
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MI->getOperand(Consts[i].first).setReg(
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AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[i].second));
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break;
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case 1:
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MI->getOperand(Consts[i].first).setReg(
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AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[i].second));
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break;
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default:
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llvm_unreachable("Wrong Cache Line");
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}
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}
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return true;
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}
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MachineBasicBlock::iterator
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MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const {
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MachineBasicBlock::iterator ClauseHead = I;
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std::vector<std::pair<unsigned, unsigned> > KCacheBanks;
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bool PushBeforeModifier = false;
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unsigned AluInstCount = 0;
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for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
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if (IsTrivialInst(I))
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continue;
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if (!isALU(I))
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break;
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if (I->getOpcode() == AMDGPU::PRED_X) {
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if (TII->getFlagOp(I).getImm() & MO_FLAG_PUSH)
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PushBeforeModifier = true;
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AluInstCount ++;
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continue;
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}
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if (TII->isALUInstr(I->getOpcode()) &&
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!SubstituteKCacheBank(I, KCacheBanks))
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break;
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AluInstCount += OccupiedDwords(I);
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if (AluInstCount > 124)
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break;
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}
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unsigned Opcode = PushBeforeModifier ?
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AMDGPU::CF_ALU_PUSH_BEFORE : AMDGPU::CF_ALU;
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BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
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.addImm(0) // ADDR
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.addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0
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.addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1
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.addImm(KCacheBanks.empty()?0:2) // KM0
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.addImm((KCacheBanks.size() < 2)?0:2) // KM1
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.addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0
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.addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1
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.addImm(AluInstCount); // COUNT
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return I;
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}
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public:
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R600EmitClauseMarkersPass(TargetMachine &tm) : MachineFunctionPass(ID),
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TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
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virtual bool runOnMachineFunction(MachineFunction &MF) {
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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MachineBasicBlock::iterator I = MBB.begin();
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if (I->getOpcode() == AMDGPU::CF_ALU)
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continue; // BB was already parsed
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for (MachineBasicBlock::iterator E = MBB.end(); I != E;) {
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if (isALU(I))
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I = MakeALUClause(MBB, I);
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else
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++I;
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}
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}
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return false;
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}
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const char *getPassName() const {
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return "R600 Emit Clause Markers Pass";
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}
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};
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char R600EmitClauseMarkersPass::ID = 0;
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}
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llvm::FunctionPass *llvm::createR600EmitClauseMarkers(TargetMachine &TM) {
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return new R600EmitClauseMarkersPass(TM);
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}
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@ -351,9 +351,9 @@ class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
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(ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
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R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
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LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
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!strconcat(opName,
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!strconcat(" ", opName,
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"$clamp $dst$write$dst_rel$omod, "
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"$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
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"$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
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"$literal $pred_sel$last"),
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pattern,
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itin>,
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@ -392,10 +392,10 @@ class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
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R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
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R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, ABS:$src1_abs, SEL:$src1_sel,
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LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
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!strconcat(opName,
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!strconcat(" ", opName,
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"$clamp $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
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"$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
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"$src1_neg$src1_abs$src1$src1_sel$src1_abs$src1_rel, "
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"$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
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"$src1_neg$src1_abs$src1$src1_abs$src1_rel, "
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"$literal $pred_sel$last"),
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pattern,
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itin>,
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@ -430,10 +430,10 @@ class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
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R600_Reg32:$src1, NEG:$src1_neg, REL:$src1_rel, SEL:$src1_sel,
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R600_Reg32:$src2, NEG:$src2_neg, REL:$src2_rel, SEL:$src2_sel,
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LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal),
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!strconcat(opName, "$clamp $dst$dst_rel, "
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"$src0_neg$src0$src0_sel$src0_rel, "
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"$src1_neg$src1$src1_sel$src1_rel, "
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"$src2_neg$src2$src2_sel$src2_rel, "
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!strconcat(" ", opName, "$clamp $dst$dst_rel, "
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"$src0_neg$src0$src0_rel, "
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"$src1_neg$src1$src1_rel, "
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"$src2_neg$src2$src2_rel, "
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"$literal $pred_sel$last"),
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pattern,
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itin>,
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@ -765,6 +765,67 @@ class ExportBufInst : InstR600ISA<(
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let Inst{63-32} = Word1;
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}
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions
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//===----------------------------------------------------------------------===//
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class CF_ALU_WORD0 {
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field bits<32> Word0;
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bits<22> ADDR;
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bits<4> KCACHE_BANK0;
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bits<4> KCACHE_BANK1;
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bits<2> KCACHE_MODE0;
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let Word0{21-0} = ADDR;
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let Word0{25-22} = KCACHE_BANK0;
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let Word0{29-26} = KCACHE_BANK1;
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let Word0{31-30} = KCACHE_MODE0;
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}
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class CF_ALU_WORD1 {
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field bits<32> Word1;
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bits<2> KCACHE_MODE1;
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bits<8> KCACHE_ADDR0;
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bits<8> KCACHE_ADDR1;
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bits<7> COUNT;
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bits<1> ALT_CONST;
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bits<4> CF_INST;
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bits<1> WHOLE_QUAD_MODE;
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bits<1> BARRIER;
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let Word1{1-0} = KCACHE_MODE1;
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let Word1{9-2} = KCACHE_ADDR0;
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let Word1{17-10} = KCACHE_ADDR1;
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let Word1{24-18} = COUNT;
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let Word1{25} = ALT_CONST;
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let Word1{29-26} = CF_INST;
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let Word1{30} = WHOLE_QUAD_MODE;
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let Word1{31} = BARRIER;
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}
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class ALU_CLAUSE<bits<4> inst, string OpName> : AMDGPUInst <(outs),
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(ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, i32imm:$KCACHE_MODE0, i32imm:$KCACHE_MODE1,
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i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, i32imm:$COUNT),
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!strconcat(OpName, " $COUNT, @$ADDR, "
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"KC0[CB$KCACHE_BANK0:$KCACHE_ADDR0-$KCACHE_ADDR0+32]"
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", KC1[CB$KCACHE_BANK1:$KCACHE_ADDR1-$KCACHE_ADDR1+32]"),
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[] >, CF_ALU_WORD0, CF_ALU_WORD1 {
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field bits<64> Inst;
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let CF_INST = inst;
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let ALT_CONST = 0;
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let WHOLE_QUAD_MODE = 0;
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let BARRIER = 1;
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let Inst{31-0} = Word0;
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let Inst{63-32} = Word1;
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}
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def CF_ALU : ALU_CLAUSE<8, "ALU">;
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def CF_ALU_PUSH_BEFORE : ALU_CLAUSE<9, "ALU_PUSH_BEFORE">;
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let Predicates = [isR600toCayman] in {
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//===----------------------------------------------------------------------===//
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@ -43,6 +43,37 @@ foreach Index = 0-127 in {
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Index>;
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}
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// KCACHE_BANK0
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foreach Index = 159-128 in {
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foreach Chan = [ "X", "Y", "Z", "W" ] in {
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// 32-bit Temporary Registers
|
||||
def KC0_#Index#_#Chan : R600RegWithChan <"KC0["#Index#"-128]."#Chan, Index, Chan>;
|
||||
}
|
||||
// 128-bit Temporary Registers
|
||||
def KC0_#Index#_XYZW : R600Reg_128 <"KC0["#Index#"-128].XYZW",
|
||||
[!cast<Register>("KC0_"#Index#"_X"),
|
||||
!cast<Register>("KC0_"#Index#"_Y"),
|
||||
!cast<Register>("KC0_"#Index#"_Z"),
|
||||
!cast<Register>("KC0_"#Index#"_W")],
|
||||
Index>;
|
||||
}
|
||||
|
||||
// KCACHE_BANK1
|
||||
foreach Index = 191-160 in {
|
||||
foreach Chan = [ "X", "Y", "Z", "W" ] in {
|
||||
// 32-bit Temporary Registers
|
||||
def KC1_#Index#_#Chan : R600RegWithChan <"KC1["#Index#"-160]."#Chan, Index, Chan>;
|
||||
}
|
||||
// 128-bit Temporary Registers
|
||||
def KC1_#Index#_XYZW : R600Reg_128 <"KC1["#Index#"-160].XYZW",
|
||||
[!cast<Register>("KC1_"#Index#"_X"),
|
||||
!cast<Register>("KC1_"#Index#"_Y"),
|
||||
!cast<Register>("KC1_"#Index#"_Z"),
|
||||
!cast<Register>("KC1_"#Index#"_W")],
|
||||
Index>;
|
||||
}
|
||||
|
||||
|
||||
// Array Base Register holding input in FS
|
||||
foreach Index = 448-480 in {
|
||||
def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>;
|
||||
@ -80,6 +111,38 @@ def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X",
|
||||
|
||||
} // End isAllocatable = 0
|
||||
|
||||
def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(add (sequence "KC0_%u_X", 128, 159))>;
|
||||
|
||||
def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(add (sequence "KC0_%u_Y", 128, 159))>;
|
||||
|
||||
def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(add (sequence "KC0_%u_Z", 128, 159))>;
|
||||
|
||||
def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(add (sequence "KC0_%u_W", 128, 159))>;
|
||||
|
||||
def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(interleave R600_KC0_X, R600_KC0_Y,
|
||||
R600_KC0_Z, R600_KC0_W)>;
|
||||
|
||||
def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(add (sequence "KC1_%u_X", 160, 191))>;
|
||||
|
||||
def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(add (sequence "KC1_%u_Y", 160, 191))>;
|
||||
|
||||
def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(add (sequence "KC1_%u_Z", 160, 191))>;
|
||||
|
||||
def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(add (sequence "KC1_%u_W", 160, 191))>;
|
||||
|
||||
def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(interleave R600_KC1_X, R600_KC1_Y,
|
||||
R600_KC1_Z, R600_KC1_W)>;
|
||||
|
||||
def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
|
||||
(add (sequence "T%u_X", 0, 127), AR_X)>;
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
|
||||
|
||||
; CHECK: @main1
|
||||
; CHECK: MOV T{{[0-9]+\.[XYZW], CBuf0\[[0-9]+\]\.[XYZW]}}
|
||||
; CHECK: MOV T{{[0-9]+\.[XYZW], KC0}}
|
||||
define void @main1() {
|
||||
main_body:
|
||||
%0 = load <4 x float> addrspace(8)* null
|
||||
|
||||
Loading…
Reference in New Issue
Block a user