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Spill / restore should avoid modifying the condition register.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-02-07 00:06:56 +00:00
parent c67da0cf13
commit 8e59ea998f
4 changed files with 64 additions and 36 deletions
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lib/Target/ARM/ARMInstrInfo.cpp
+2 -2
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@@ -83,7 +83,7 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co
return MI->getOperand(0).getReg();
}
break;
case ARM::tLDRspi:
case ARM::tRestore:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImmedValue() == 0) {
@@ -117,7 +117,7 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con
return MI->getOperand(0).getReg();
}
break;
case ARM::tSTRspi:
case ARM::tSpill:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImmedValue() == 0) {