Eliminate special-casing 14-bit immediate load/store opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15677 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-08-12 02:51:38 +00:00
parent a5de823844
commit 8e63dcebcc

View File

@ -570,8 +570,11 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
}
O << TII.getName(Opcode) << " ";
if (Opcode == PPC::LD || Opcode == PPC::LWA ||
Opcode == PPC::STDU || Opcode == PPC::STDUX) {
if (Opcode == PPC::BLR || Opcode == PPC::NOP) {
// FIXME: BuildMI() should handle 0 params
O << "\n";
} else if (ArgCount == 3 &&
(ArgType[1] == PPCII::Disimm16 || ArgType[1] == PPCII::Disimm14)) {
printOp(MI->getOperand(0));
O << ", ";
MachineOperand MO = MI->getOperand(1);
@ -582,20 +585,6 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
O << "(";
printOp(MI->getOperand(2));
O << ")\n";
} else if (Opcode == PPC::BLR || Opcode == PPC::NOP) {
// FIXME: BuildMI() should handle 0 params
O << "\n";
} else if (ArgCount == 3 && ArgType[1] == PPCII::Disimm16) {
printOp(MI->getOperand(0));
O << ", ";
printImmOp(MI->getOperand(1), ArgType[1]);
O << "(";
if (MI->getOperand(2).hasAllocatedReg() &&
MI->getOperand(2).getReg() == PPC::R0)
O << "0";
else
printOp(MI->getOperand(2));
O << ")\n";
} else {
for (i = 0; i < ArgCount; ++i) {
// addi and friends