mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
[mips] Refactor LUI instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170944 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
35242e27c5
commit
8e719fac46
@ -94,7 +94,7 @@ def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>,
|
||||
ADDI_FM<0xd>;
|
||||
def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>,
|
||||
ADDI_FM<0xe>;
|
||||
def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
|
||||
def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
|
||||
|
||||
/// Arithmetic Instructions (3-Operand, R-Type)
|
||||
def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>;
|
||||
|
@ -356,6 +356,18 @@ class CLO_FM<bits<6> funct> {
|
||||
let rt = rd;
|
||||
}
|
||||
|
||||
class LUI_FM {
|
||||
bits<5> rt;
|
||||
bits<16> imm16;
|
||||
|
||||
bits<32> Inst;
|
||||
|
||||
let Inst{31-26} = 0xf;
|
||||
let Inst{25-21} = 0;
|
||||
let Inst{20-16} = rt;
|
||||
let Inst{15-0} = imm16;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// FLOATING POINT INSTRUCTION FORMATS
|
||||
|
@ -388,10 +388,9 @@ class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>:
|
||||
[(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>;
|
||||
|
||||
// Load Upper Imediate
|
||||
class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
|
||||
FI<op, (outs RC:$rt), (ins Imm:$imm16),
|
||||
!strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove {
|
||||
let rs = 0;
|
||||
class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
|
||||
InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
|
||||
[], IIAlu, FrmI>, IsAsCheapAsAMove {
|
||||
let neverHasSideEffects = 1;
|
||||
let isReMaterializable = 1;
|
||||
}
|
||||
@ -846,7 +845,7 @@ def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>;
|
||||
def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>;
|
||||
def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>;
|
||||
def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>;
|
||||
def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
|
||||
def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
|
||||
|
||||
/// Arithmetic Instructions (3-Operand, R-Type)
|
||||
def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>;
|
||||
|
Loading…
Reference in New Issue
Block a user