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Emit the warning about the register list not being in ascending order only once.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-09 23:45:59 +00:00
parent 18f601820c
commit 8e8b18bcfa
1 changed files with 8 additions and 5 deletions
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13
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -512,24 +512,27 @@ ARMOperand *ARMAsmParser::ParseRegisterList() {
SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
RI = Registers.begin(), RE = Registers.end();
unsigned HighRegNum = RI->first;
DenseMap<unsigned, bool> RegMap;
RegMap[RI->first] = true;
unsigned HighRegNum = RI->first;
bool EmittedWarning = false;
for (++RI; RI != RE; ++RI) {
const std::pair<unsigned, SMLoc> &RegInfo = *RI;
unsigned Reg = RegInfo.first;
if (RegMap[RegInfo.first]) {
if (RegMap[Reg]) {
Error(RegInfo.second, "register duplicated in register list");
return 0;
}
if (RegInfo.first < HighRegNum)
if (!EmittedWarning && Reg < HighRegNum)
Warning(RegInfo.second,
"register not in ascending order in register list");
RegMap[RegInfo.first] = true;
HighRegNum = std::max(RegInfo.first, HighRegNum);
RegMap[Reg] = true;
HighRegNum = std::max(Reg, HighRegNum);
}
return ARMOperand::CreateRegList(Registers, S, E);