mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Const-ify several TargetInstrInfo methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
fcab2bd2f3
commit
8e8b8a223c
@ -102,6 +102,8 @@ public:
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MachineInstr& front() { return Insts.front(); }
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MachineInstr& front() { return Insts.front(); }
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MachineInstr& back() { return Insts.back(); }
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MachineInstr& back() { return Insts.back(); }
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const MachineInstr& front() const { return Insts.front(); }
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const MachineInstr& back() const { return Insts.back(); }
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iterator begin() { return Insts.begin(); }
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iterator begin() { return Insts.begin(); }
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const_iterator begin() const { return Insts.begin(); }
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const_iterator begin() const { return Insts.begin(); }
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@ -288,7 +288,7 @@ public:
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/// stream.
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/// stream.
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const {
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int FrameIndex) const {
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return 0;
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return 0;
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}
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}
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@ -298,7 +298,7 @@ public:
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/// stack slot.
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/// stack slot.
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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MachineInstr* LoadMI) const {
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return 0;
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return 0;
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}
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}
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@ -306,8 +306,8 @@ public:
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/// canFoldMemoryOperand - Returns true if the specified load / store is
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/// canFoldMemoryOperand - Returns true if the specified load / store is
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/// folding is possible.
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/// folding is possible.
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virtual
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virtual
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bool canFoldMemoryOperand(MachineInstr *MI,
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bool canFoldMemoryOperand(const MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops) const{
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const SmallVectorImpl<unsigned> &Ops) const {
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return false;
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return false;
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}
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}
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@ -338,7 +338,7 @@ public:
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/// fall-through into its successor block. This is primarily used when a
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/// fall-through into its successor block. This is primarily used when a
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/// branch is unanalyzable. It is useful for things like unconditional
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/// branch is unanalyzable. It is useful for things like unconditional
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/// indirect branches (jump tables).
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/// indirect branches (jump tables).
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virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
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virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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return false;
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return false;
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}
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}
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@ -663,7 +663,7 @@ bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr *MI,
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MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FI) const {
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int FI) const {
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if (Ops.size() != 1) return NULL;
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if (Ops.size() != 1) return NULL;
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@ -747,8 +747,8 @@ MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF,
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return NewMI;
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return NewMI;
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}
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}
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bool ARMInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
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bool ARMInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops) const {
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const SmallVectorImpl<unsigned> &Ops) const {
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if (Ops.size() != 1) return false;
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if (Ops.size() != 1) return false;
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unsigned OpNum = Ops[0];
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unsigned OpNum = Ops[0];
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@ -780,7 +780,7 @@ bool ARMInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
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return false;
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return false;
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}
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}
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bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
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bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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if (MBB.empty()) return false;
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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switch (MBB.back().getOpcode()) {
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@ -198,20 +198,20 @@ public:
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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int FrameIndex) const;
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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MachineInstr* LoadMI) const {
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return 0;
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return 0;
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}
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}
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virtual bool canFoldMemoryOperand(MachineInstr *MI,
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virtual bool canFoldMemoryOperand(const MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops) const;
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const SmallVectorImpl<unsigned> &Ops) const;
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virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
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virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
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virtual
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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@ -255,7 +255,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr *AlphaInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr *MI,
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MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const {
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int FrameIndex) const {
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if (Ops.size() != 1) return NULL;
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if (Ops.size() != 1) return NULL;
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@ -408,7 +408,7 @@ void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
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.addReg(Alpha::R31);
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.addReg(Alpha::R31);
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}
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}
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bool AlphaInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
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bool AlphaInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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if (MBB.empty()) return false;
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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switch (MBB.back().getOpcode()) {
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@ -69,12 +69,12 @@ public:
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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int FrameIndex) const;
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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MachineInstr* LoadMI) const {
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return 0;
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return 0;
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}
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}
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@ -85,7 +85,7 @@ public:
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unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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void insertNoop(MachineBasicBlock &MBB,
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void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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MachineBasicBlock::iterator MI) const;
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bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
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bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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};
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};
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@ -399,7 +399,7 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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MachineInstr *
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MachineInstr *
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SPUInstrInfo::foldMemoryOperand(MachineFunction &MF,
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SPUInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr *MI,
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MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const
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int FrameIndex) const
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{
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{
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#if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
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#if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
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@ -79,13 +79,13 @@ namespace llvm {
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//! Fold spills into load/store instructions
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//! Fold spills into load/store instructions
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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int FrameIndex) const;
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//! Fold any load/store to an operand
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//! Fold any load/store to an operand
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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MachineInstr* LoadMI) const {
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return 0;
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return 0;
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}
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}
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@ -281,7 +281,7 @@ void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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MachineInstr *MipsInstrInfo::
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MachineInstr *MipsInstrInfo::
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foldMemoryOperand(MachineFunction &MF,
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foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops, int FI) const
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const SmallVectorImpl<unsigned> &Ops, int FI) const
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{
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{
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if (Ops.size() != 1) return NULL;
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if (Ops.size() != 1) return NULL;
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@ -602,7 +602,7 @@ RemoveBranch(MachineBasicBlock &MBB) const
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/// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
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/// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
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/// fall-through into its successor block.
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/// fall-through into its successor block.
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bool MipsInstrInfo::
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bool MipsInstrInfo::
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BlockHasNoFallThrough(MachineBasicBlock &MBB) const
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BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
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{
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{
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if (MBB.empty()) return false;
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if (MBB.empty()) return false;
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@ -196,17 +196,17 @@ public:
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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int FrameIndex) const;
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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MachineInstr* LoadMI) const {
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return 0;
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return 0;
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}
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}
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virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
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virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
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virtual
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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@ -657,7 +657,7 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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/// copy instructions, turning them into load/store instructions.
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/// copy instructions, turning them into load/store instructions.
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MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr *MI,
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MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const {
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int FrameIndex) const {
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if (Ops.size() != 1) return NULL;
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if (Ops.size() != 1) return NULL;
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@ -730,8 +730,8 @@ MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
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return NewMI;
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return NewMI;
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}
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}
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bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
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bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops) const {
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const SmallVectorImpl<unsigned> &Ops) const {
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if (Ops.size() != 1) return false;
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if (Ops.size() != 1) return false;
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// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
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// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
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@ -751,7 +751,7 @@ bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
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}
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}
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bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
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bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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if (MBB.empty()) return false;
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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switch (MBB.back().getOpcode()) {
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@ -142,20 +142,20 @@ public:
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/// copy instructions, turning them into load/store instructions.
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/// copy instructions, turning them into load/store instructions.
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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int FrameIndex) const;
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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MachineInstr* LoadMI) const {
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return 0;
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return 0;
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}
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}
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virtual bool canFoldMemoryOperand(MachineInstr *MI,
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virtual bool canFoldMemoryOperand(const MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops) const;
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const SmallVectorImpl<unsigned> &Ops) const;
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virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
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virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
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virtual
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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@ -227,7 +227,7 @@ void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FI) const {
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int FI) const {
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if (Ops.size() != 1) return NULL;
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if (Ops.size() != 1) return NULL;
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@ -96,12 +96,12 @@ public:
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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int FrameIndex) const;
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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MachineInstr* LoadMI) const {
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return 0;
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return 0;
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}
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}
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@ -1543,7 +1543,7 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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}
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}
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static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
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static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
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MachineOperand &MO) {
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const MachineOperand &MO) {
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if (MO.isReg())
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if (MO.isReg())
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MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
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MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
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MO.isKill(), MO.isDead(), MO.getSubReg());
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MO.isKill(), MO.isDead(), MO.getSubReg());
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@ -1872,7 +1872,7 @@ bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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}
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}
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static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
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static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
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SmallVector<MachineOperand,4> &MOs,
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const SmallVector<MachineOperand,4> &MOs,
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MachineInstr *MI, const TargetInstrInfo &TII) {
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MachineInstr *MI, const TargetInstrInfo &TII) {
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// Create the base instruction with the memory operand as the first part.
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// Create the base instruction with the memory operand as the first part.
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MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
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MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
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@ -1898,7 +1898,7 @@ static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
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static MachineInstr *FuseInst(MachineFunction &MF,
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static MachineInstr *FuseInst(MachineFunction &MF,
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unsigned Opcode, unsigned OpNo,
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unsigned Opcode, unsigned OpNo,
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SmallVector<MachineOperand,4> &MOs,
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const SmallVector<MachineOperand,4> &MOs,
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MachineInstr *MI, const TargetInstrInfo &TII) {
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MachineInstr *MI, const TargetInstrInfo &TII) {
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MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
|
MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
|
||||||
MachineInstrBuilder MIB(NewMI);
|
MachineInstrBuilder MIB(NewMI);
|
||||||
@ -1920,7 +1920,7 @@ static MachineInstr *FuseInst(MachineFunction &MF,
|
|||||||
}
|
}
|
||||||
|
|
||||||
static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
|
static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
|
||||||
SmallVector<MachineOperand,4> &MOs,
|
const SmallVector<MachineOperand,4> &MOs,
|
||||||
MachineInstr *MI) {
|
MachineInstr *MI) {
|
||||||
MachineFunction &MF = *MI->getParent()->getParent();
|
MachineFunction &MF = *MI->getParent()->getParent();
|
||||||
MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode));
|
MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode));
|
||||||
@ -1936,7 +1936,7 @@ static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
|
|||||||
MachineInstr*
|
MachineInstr*
|
||||||
X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
|
X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
|
||||||
MachineInstr *MI, unsigned i,
|
MachineInstr *MI, unsigned i,
|
||||||
SmallVector<MachineOperand,4> &MOs) const {
|
const SmallVector<MachineOperand,4> &MOs) const{
|
||||||
const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
|
const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
|
||||||
bool isTwoAddrFold = false;
|
bool isTwoAddrFold = false;
|
||||||
unsigned NumOps = MI->getDesc().getNumOperands();
|
unsigned NumOps = MI->getDesc().getNumOperands();
|
||||||
@ -1995,7 +1995,7 @@ X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
|
|||||||
|
|
||||||
MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
|
MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
|
||||||
MachineInstr *MI,
|
MachineInstr *MI,
|
||||||
SmallVectorImpl<unsigned> &Ops,
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
int FrameIndex) const {
|
int FrameIndex) const {
|
||||||
// Check switch flag
|
// Check switch flag
|
||||||
if (NoFusing) return NULL;
|
if (NoFusing) return NULL;
|
||||||
@ -2042,7 +2042,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
|
|||||||
|
|
||||||
MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
|
MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
|
||||||
MachineInstr *MI,
|
MachineInstr *MI,
|
||||||
SmallVectorImpl<unsigned> &Ops,
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
MachineInstr *LoadMI) const {
|
MachineInstr *LoadMI) const {
|
||||||
// Check switch flag
|
// Check switch flag
|
||||||
if (NoFusing) return NULL;
|
if (NoFusing) return NULL;
|
||||||
@ -2093,8 +2093,8 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI,
|
bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
|
||||||
SmallVectorImpl<unsigned> &Ops) const {
|
const SmallVectorImpl<unsigned> &Ops) const {
|
||||||
// Check switch flag
|
// Check switch flag
|
||||||
if (NoFusing) return 0;
|
if (NoFusing) return 0;
|
||||||
|
|
||||||
@ -2350,7 +2350,7 @@ unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
|
|||||||
return I->second.first;
|
return I->second.first;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
|
||||||
if (MBB.empty()) return false;
|
if (MBB.empty()) return false;
|
||||||
|
|
||||||
switch (MBB.back().getOpcode()) {
|
switch (MBB.back().getOpcode()) {
|
||||||
|
@ -359,7 +359,7 @@ public:
|
|||||||
/// references has been changed.
|
/// references has been changed.
|
||||||
virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
|
virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
|
||||||
MachineInstr* MI,
|
MachineInstr* MI,
|
||||||
SmallVectorImpl<unsigned> &Ops,
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
int FrameIndex) const;
|
int FrameIndex) const;
|
||||||
|
|
||||||
/// foldMemoryOperand - Same as the previous version except it allows folding
|
/// foldMemoryOperand - Same as the previous version except it allows folding
|
||||||
@ -367,12 +367,13 @@ public:
|
|||||||
/// stack slot.
|
/// stack slot.
|
||||||
virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
|
virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
|
||||||
MachineInstr* MI,
|
MachineInstr* MI,
|
||||||
SmallVectorImpl<unsigned> &Ops,
|
const SmallVectorImpl<unsigned> &Ops,
|
||||||
MachineInstr* LoadMI) const;
|
MachineInstr* LoadMI) const;
|
||||||
|
|
||||||
/// canFoldMemoryOperand - Returns true if the specified load / store is
|
/// canFoldMemoryOperand - Returns true if the specified load / store is
|
||||||
/// folding is possible.
|
/// folding is possible.
|
||||||
virtual bool canFoldMemoryOperand(MachineInstr*, SmallVectorImpl<unsigned> &) const;
|
virtual bool canFoldMemoryOperand(const MachineInstr*,
|
||||||
|
const SmallVectorImpl<unsigned> &) const;
|
||||||
|
|
||||||
/// unfoldMemoryOperand - Separate a single instruction which folded a load or
|
/// unfoldMemoryOperand - Separate a single instruction which folded a load or
|
||||||
/// a store or a load and a store into two or more instruction. If this is
|
/// a store or a load and a store into two or more instruction. If this is
|
||||||
@ -391,7 +392,7 @@ public:
|
|||||||
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
||||||
bool UnfoldLoad, bool UnfoldStore) const;
|
bool UnfoldLoad, bool UnfoldStore) const;
|
||||||
|
|
||||||
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
|
virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
|
||||||
virtual
|
virtual
|
||||||
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
||||||
|
|
||||||
@ -431,7 +432,7 @@ private:
|
|||||||
MachineInstr* foldMemoryOperand(MachineFunction &MF,
|
MachineInstr* foldMemoryOperand(MachineFunction &MF,
|
||||||
MachineInstr* MI,
|
MachineInstr* MI,
|
||||||
unsigned OpNum,
|
unsigned OpNum,
|
||||||
SmallVector<MachineOperand,4> &MOs) const;
|
const SmallVector<MachineOperand,4> &MOs) const;
|
||||||
};
|
};
|
||||||
|
|
||||||
} // End llvm namespace
|
} // End llvm namespace
|
||||||
|
Loading…
Reference in New Issue
Block a user