From 8ea13c6233d7dded98d933b435f2727a38149a70 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Mon, 19 Jul 2004 05:55:50 +0000
Subject: [PATCH] Two changes, both very significant:
* vreg <-> vreg joining now works, enable it unconditionally when joining
is enabled (which is the default).
* Fix a serious pessimization of spill code where we were saying that a
spilled DEF operand was live into the subsequent instruction. This allows
for substantially better code when spilling starts to happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14993 91177308-0d34-0410-b5e6-96231b3b80d8
---
lib/CodeGen/LiveIntervalAnalysis.cpp | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 9687e589812..ee988b10a40 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -60,11 +60,6 @@ namespace {
EnableJoining("join-liveintervals",
cl::desc("Join compatible live intervals"),
cl::init(true));
-
- cl::opt<bool>
- EnableVirtVirtJoining("join-liveintervals-virtvirtjoining",
- cl::desc("Join live intervals for virtreg pairs (buggy)"),
- cl::init(false));
};
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
@@ -251,7 +246,7 @@ std::vector<LiveInterval*> LiveIntervals::addIntervalsForSpills(
// use of the next instruction. Otherwise we end
// after the use of this instruction.
unsigned end = 1 + (mop.isDef() ?
- getUseIndex(index+InstrSlots::NUM) :
+ getStoreIndex(index) :
getUseIndex(index));
// create a new register for this spill
@@ -545,11 +540,7 @@ void LiveIntervals::joinIntervals()
Intervals::iterator intB = r2iB->second;
// both A and B are virtual registers
-
- // FIXME: coallescing two virtual registers together is
- // apparently broken.
- if (EnableVirtVirtJoining &&
- MRegisterInfo::isVirtualRegister(intA->reg) &&
+ if (MRegisterInfo::isVirtualRegister(intA->reg) &&
MRegisterInfo::isVirtualRegister(intB->reg)) {
const TargetRegisterClass *rcA, *rcB;