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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42377 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-09-26 21:38:03 +00:00
parent 42d60274ea
commit 8ed3ffee53
1 changed files with 7 additions and 1 deletions
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8
include/llvm/CodeGen/ScheduleDAG.h
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@ -33,6 +33,7 @@ namespace llvm {
class TargetInstrInfo; class TargetInstrInfo;
class TargetInstrDescriptor; class TargetInstrDescriptor;
class TargetMachine; class TargetMachine;
class TargetRegisterClass;
/// HazardRecognizer - This determines whether or not an instruction can be /// HazardRecognizer - This determines whether or not an instruction can be
/// issued this cycle, and whether or not a noop needs to be inserted to handle /// issued this cycle, and whether or not a noop needs to be inserted to handle
@ -124,6 +125,8 @@ namespace llvm {
unsigned Cycle; // Once scheduled, the cycle of the op. unsigned Cycle; // Once scheduled, the cycle of the op.
unsigned Depth; // Node depth; unsigned Depth; // Node depth;
unsigned Height; // Node height; unsigned Height; // Node height;
const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
const TargetRegisterClass *CopySrcRC;
SUnit(SDNode *node, unsigned nodenum) SUnit(SDNode *node, unsigned nodenum)
: Node(node), InstanceNo(0), NodeNum(nodenum), Latency(0), : Node(node), InstanceNo(0), NodeNum(nodenum), Latency(0),
@ -131,7 +134,8 @@ namespace llvm {
NumChainPredsLeft(0), NumChainSuccsLeft(0), NumChainPredsLeft(0), NumChainSuccsLeft(0),
isTwoAddress(false), isCommutable(false), hasImplicitDefs(false), isTwoAddress(false), isCommutable(false), hasImplicitDefs(false),
isPending(false), isAvailable(false), isScheduled(false), isPending(false), isAvailable(false), isScheduled(false),
CycleBound(0), Cycle(0), Depth(0), Height(0) {} CycleBound(0), Cycle(0), Depth(0), Height(0),
CopyDstRC(NULL), CopySrcRC(NULL) {}
/// addPred - This adds the specified node as a pred of the current node if /// addPred - This adds the specified node as a pred of the current node if
/// not already. This returns true if this is a new pred. /// not already. This returns true if this is a new pred.
@ -332,6 +336,8 @@ namespace llvm {
/// ///
void EmitNoop(); void EmitNoop();
void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
/// implicit physical register output. /// implicit physical register output.
void EmitCopyFromReg(SDNode *Node, unsigned ResNo, unsigned InstNo, void EmitCopyFromReg(SDNode *Node, unsigned ResNo, unsigned InstNo,