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Prevent ARM assembler from losing a right shift by #32 applied to a register

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Barton 2012-07-09 16:31:14 +00:00
parent c985e6ece6
commit 8ed97ef5f6
2 changed files with 36 additions and 1 deletions
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4
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -7247,7 +7247,9 @@ processInstruction(MCInst &Inst,
case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
}
// If the shift is by zero, use the non-shifted instruction definition.
if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) {
// The exception is for right shifts, where 0 == 32
if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
!(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
MCInst TmpInst;
TmpInst.setOpcode(newOpc);
TmpInst.addOperand(Inst.getOperand(0));

33
test/MC/ARM/basic-arm-instructions.s
View File

@ -206,6 +206,11 @@ Lforward:
@ CHECK: sub r0, r0, #4 @ encoding: [0x04,0x00,0x40,0xe2]
@ CHECK: sub r4, r5, #21 @ encoding: [0x15,0x40,0x45,0xe2]
@ Test right shift by 32, which is encoded as 0
add r3, r1, r2, lsr #32
add r3, r1, r2, asr #32
@ CHECK: add r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0x81,0xe0]
@ CHECK: add r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x81,0xe0]
@------------------------------------------------------------------------------
@ AND
@ -265,6 +270,12 @@ Lforward:
@ CHECK: and r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0x06,0xe0]
@ CHECK: and r10, r10, r1, rrx @ encoding: [0x61,0xa0,0x0a,0xe0]
@ Test right shift by 32, which is encoded as 0
and r3, r1, r2, lsr #32
and r3, r1, r2, asr #32
@ CHECK: and r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0x01,0xe0]
@ CHECK: and r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x01,0xe0]
@------------------------------------------------------------------------------
@ ASR
@------------------------------------------------------------------------------
@ -368,6 +379,12 @@ Lforward:
@ CHECK: bic r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0xc6,0xe1]
@ CHECK: bic r10, r10, r1, rrx @ encoding: [0x61,0xa0,0xca,0xe1]
@ Test right shift by 32, which is encoded as 0
bic r3, r1, r2, lsr #32
bic r3, r1, r2, asr #32
@ CHECK: bic r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0xc1,0xe1]
@ CHECK: bic r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0xc1,0xe1]
@------------------------------------------------------------------------------
@ BKPT
@------------------------------------------------------------------------------
@ -664,6 +681,11 @@ Lforward:
@ CHECK: eor r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x26,0xe0]
@ CHECK: eor r4, r4, r5, rrx @ encoding: [0x65,0x40,0x24,0xe0]
@ Test right shift by 32, which is encoded as 0
eor r3, r1, r2, lsr #32
eor r3, r1, r2, asr #32
@ CHECK: eor r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0x21,0xe0]
@ CHECK: eor r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x21,0xe0]
@------------------------------------------------------------------------------
@ ISB
@ -1211,6 +1233,12 @@ Lforward:
@ CHECK: orrslt r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x96,0xb1]
@ CHECK: orrsgt r4, r4, r5, rrx @ encoding: [0x65,0x40,0x94,0xc1]
@ Test right shift by 32, which is encoded as 0
orr r3, r1, r2, lsr #32
orr r3, r1, r2, asr #32
@ CHECK: orr r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0x81,0xe1]
@ CHECK: orr r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x81,0xe1]
@------------------------------------------------------------------------------
@ PKH
@------------------------------------------------------------------------------
@ -2216,6 +2244,11 @@ Lforward:
@ CHECK: sub r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x46,0xe0]
@ CHECK: sub r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x46,0xe0]
@ Test right shift by 32, which is encoded as 0
sub r3, r1, r2, lsr #32
sub r3, r1, r2, asr #32
@ CHECK: sub r3, r1, r2, lsr #32 @ encoding: [0x22,0x30,0x41,0xe0]
@ CHECK: sub r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x41,0xe0]
@------------------------------------------------------------------------------
@ SVC