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Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit
incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91749 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Callanan
354
lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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354
lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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/*===- X86DisassemblerDecoderCommon.h - Disassembler decoder -------*- C -*-==*
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*
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* The LLVM Compiler Infrastructure
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*
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* This file is distributed under the University of Illinois Open Source
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* License. See LICENSE.TXT for details.
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*
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*===----------------------------------------------------------------------===*
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*
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* This file is part of the X86 Disassembler.
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* It contains common definitions used by both the disassembler and the table
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* generator.
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* Documentation for the disassembler can be found in X86Disassembler.h.
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*
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*===----------------------------------------------------------------------===*/
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/*
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* This header file provides those definitions that need to be shared between
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* the decoder and the table generator in a C-friendly manner.
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*/
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#ifndef X86DISASSEMBLERDECODERCOMMON_H
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#define X86DISASSEMBLERDECODERCOMMON_H
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#include "llvm/System/DataTypes.h"
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#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
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#define CONTEXTS_SYM x86DisassemblerContexts
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#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
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#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
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#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
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#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
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#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
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#define CONTEXTS_STR "x86DisassemblerContexts"
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#define ONEBYTE_STR "x86DisassemblerOneByteOpcodes"
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#define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes"
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#define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes"
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#define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes"
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/*
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* Attributes of an instruction that must be known before the opcode can be
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* processed correctly. Most of these indicate the presence of particular
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* prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
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*/
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#define ATTRIBUTE_BITS \
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ENUM_ENTRY(ATTR_NONE, 0x00) \
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ENUM_ENTRY(ATTR_64BIT, 0x01) \
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ENUM_ENTRY(ATTR_XS, 0x02) \
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ENUM_ENTRY(ATTR_XD, 0x04) \
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ENUM_ENTRY(ATTR_REXW, 0x08) \
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ENUM_ENTRY(ATTR_OPSIZE, 0x10)
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#define ENUM_ENTRY(n, v) n = v,
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enum attributeBits {
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ATTRIBUTE_BITS
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ATTR_max
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};
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#undef ENUM_ENTRY
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/*
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* Combinations of the above attributes that are relevant to instruction
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* decode. Although other combinations are possible, they can be reduced to
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* these without affecting the ultimately decoded instruction.
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*/
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/* Class name Rank Rationale for rank assignment */
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#define INSTRUCTION_CONTEXTS \
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ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
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ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \
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"64-bit mode but no more") \
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ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
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"operands change width") \
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ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \
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"but not the operands") \
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ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \
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"but not the operands") \
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ENUM_ENTRY(IC_64BIT_REXW, 4, "requires a REX.W prefix, so operands "\
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"change width; overrides IC_OPSIZE") \
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ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \
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ENUM_ENTRY(IC_64BIT_XD, 5, "XD instructions are SSE; REX.W is " \
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"secondary") \
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ENUM_ENTRY(IC_64BIT_XS, 5, "Just as meaningful as IC_64BIT_XD") \
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ENUM_ENTRY(IC_64BIT_REXW_XS, 6, "OPSIZE could mean a different " \
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"opcode") \
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ENUM_ENTRY(IC_64BIT_REXW_XD, 6, "Just as meaningful as " \
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"IC_64BIT_REXW_XS") \
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ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 7, "The Dynamic Duo! Prefer over all " \
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"else because this changes most " \
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"operands' meaning")
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#define ENUM_ENTRY(n, r, d) n,
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typedef enum {
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INSTRUCTION_CONTEXTS
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IC_max
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} InstructionContext;
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#undef ENUM_ENTRY
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/*
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* Opcode types, which determine which decode table to use, both in the Intel
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* manual and also for the decoder.
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*/
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typedef enum {
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ONEBYTE = 0,
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TWOBYTE = 1,
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THREEBYTE_38 = 2,
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THREEBYTE_3A = 3
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} OpcodeType;
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/*
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* The following structs are used for the hierarchical decode table. After
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* determining the instruction's class (i.e., which IC_* constant applies to
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* it), the decoder reads the opcode. Some instructions require specific
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* values of the ModR/M byte, so the ModR/M byte indexes into the final table.
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*
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* If a ModR/M byte is not required, "required" is left unset, and the values
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* for each instructionID are identical.
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*/
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typedef uint16_t InstrUID;
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/*
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* ModRMDecisionType - describes the type of ModR/M decision, allowing the
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* consumer to determine the number of entries in it.
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*
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* MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
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* instruction is the same.
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* MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
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* corresponds to one instruction; otherwise, it corresponds to
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* a different instruction.
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* MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
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* to a different instruction.
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*/
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#define MODRMTYPES \
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ENUM_ENTRY(MODRM_ONEENTRY) \
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ENUM_ENTRY(MODRM_SPLITRM) \
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ENUM_ENTRY(MODRM_FULL)
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#define ENUM_ENTRY(n) n,
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typedef enum {
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MODRMTYPES
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MODRM_max
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} ModRMDecisionType;
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#undef ENUM_ENTRY
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/*
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* ModRMDecision - Specifies whether a ModR/M byte is needed and (if so) which
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* instruction each possible value of the ModR/M byte corresponds to. Once
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* this information is known, we have narrowed down to a single instruction.
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*/
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struct ModRMDecision {
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uint8_t modrm_type;
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/* The macro below must be defined wherever this file is included. */
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INSTRUCTION_IDS
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};
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/*
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* OpcodeDecision - Specifies which set of ModR/M->instruction tables to look at
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* given a particular opcode.
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*/
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struct OpcodeDecision {
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struct ModRMDecision modRMDecisions[256];
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};
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/*
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* ContextDecision - Specifies which opcode->instruction tables to look at given
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* a particular context (set of attributes). Since there are many possible
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* contexts, the decoder first uses CONTEXTS_SYM to determine which context
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* applies given a specific set of attributes. Hence there are only IC_max
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* entries in this table, rather than 2^(ATTR_max).
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*/
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struct ContextDecision {
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struct OpcodeDecision opcodeDecisions[IC_max];
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};
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/*
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* Physical encodings of instruction operands.
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*/
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#define ENCODINGS \
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ENUM_ENTRY(ENCODING_NONE, "") \
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ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
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ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
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ENUM_ENTRY(ENCODING_CB, "1-byte code offset (possible new CS value)") \
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ENUM_ENTRY(ENCODING_CW, "2-byte") \
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ENUM_ENTRY(ENCODING_CD, "4-byte") \
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ENUM_ENTRY(ENCODING_CP, "6-byte") \
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ENUM_ENTRY(ENCODING_CO, "8-byte") \
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ENUM_ENTRY(ENCODING_CT, "10-byte") \
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ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \
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ENUM_ENTRY(ENCODING_IW, "2-byte") \
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ENUM_ENTRY(ENCODING_ID, "4-byte") \
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ENUM_ENTRY(ENCODING_IO, "8-byte") \
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ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \
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"the opcode byte") \
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ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
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ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
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ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
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ENUM_ENTRY(ENCODING_I, "Position on floating-point stack added to the " \
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"opcode byte") \
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\
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ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
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ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
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ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
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"opcode byte") \
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ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
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"in type")
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#define ENUM_ENTRY(n, d) n,
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typedef enum {
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ENCODINGS
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ENCODING_max
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} OperandEncoding;
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#undef ENUM_ENTRY
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/*
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* Semantic interpretations of instruction operands.
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*/
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#define TYPES \
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ENUM_ENTRY(TYPE_NONE, "") \
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ENUM_ENTRY(TYPE_REL8, "1-byte immediate address") \
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ENUM_ENTRY(TYPE_REL16, "2-byte") \
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ENUM_ENTRY(TYPE_REL32, "4-byte") \
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ENUM_ENTRY(TYPE_REL64, "8-byte") \
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ENUM_ENTRY(TYPE_PTR1616, "2+2-byte segment+offset address") \
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ENUM_ENTRY(TYPE_PTR1632, "2+4-byte") \
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ENUM_ENTRY(TYPE_PTR1664, "2+8-byte") \
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ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
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ENUM_ENTRY(TYPE_R16, "2-byte") \
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ENUM_ENTRY(TYPE_R32, "4-byte") \
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ENUM_ENTRY(TYPE_R64, "8-byte") \
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ENUM_ENTRY(TYPE_IMM8, "1-byte immediate operand") \
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ENUM_ENTRY(TYPE_IMM16, "2-byte") \
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ENUM_ENTRY(TYPE_IMM32, "4-byte") \
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ENUM_ENTRY(TYPE_IMM64, "8-byte") \
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ENUM_ENTRY(TYPE_RM8, "1-byte register or memory operand") \
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ENUM_ENTRY(TYPE_RM16, "2-byte") \
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ENUM_ENTRY(TYPE_RM32, "4-byte") \
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ENUM_ENTRY(TYPE_RM64, "8-byte") \
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ENUM_ENTRY(TYPE_M, "Memory operand") \
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ENUM_ENTRY(TYPE_M8, "1-byte") \
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ENUM_ENTRY(TYPE_M16, "2-byte") \
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ENUM_ENTRY(TYPE_M32, "4-byte") \
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ENUM_ENTRY(TYPE_M64, "8-byte") \
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ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \
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ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \
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ENUM_ENTRY(TYPE_M1632, "2+4-byte") \
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ENUM_ENTRY(TYPE_M1664, "2+8-byte") \
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ENUM_ENTRY(TYPE_M16_32, "2+4-byte two-part memory operand (LIDT, LGDT)") \
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ENUM_ENTRY(TYPE_M16_16, "2+2-byte (BOUND)") \
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ENUM_ENTRY(TYPE_M32_32, "4+4-byte (BOUND)") \
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ENUM_ENTRY(TYPE_M16_64, "2+8-byte (LIDT, LGDT)") \
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ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \
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"base)") \
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ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \
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ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \
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ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \
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ENUM_ENTRY(TYPE_SREG, "Byte with single bit set: 0 = ES, 1 = CS, " \
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"2 = SS, 3 = DS, 4 = FS, 5 = GS") \
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ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \
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ENUM_ENTRY(TYPE_M64FP, "64-bit") \
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ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \
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ENUM_ENTRY(TYPE_M16INT, "2-byte memory integer operand for use in " \
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"floating-point instructions") \
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ENUM_ENTRY(TYPE_M32INT, "4-byte") \
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ENUM_ENTRY(TYPE_M64INT, "8-byte") \
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ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
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ENUM_ENTRY(TYPE_MM, "MMX register operand") \
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ENUM_ENTRY(TYPE_MM32, "4-byte MMX register or memory operand") \
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ENUM_ENTRY(TYPE_MM64, "8-byte") \
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ENUM_ENTRY(TYPE_XMM, "XMM register operand") \
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ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \
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ENUM_ENTRY(TYPE_XMM64, "8-byte") \
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ENUM_ENTRY(TYPE_XMM128, "16-byte") \
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ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \
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ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
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ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
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ENUM_ENTRY(TYPE_CR32, "4-byte control register operand") \
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ENUM_ENTRY(TYPE_CR64, "8-byte") \
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\
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ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \
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ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
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ENUM_ENTRY(TYPE_IMMv, "Immediate operand of operand size") \
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ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
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ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
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ENUM_ENTRY(TYPE_DUP1, "operand 1") \
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ENUM_ENTRY(TYPE_DUP2, "operand 2") \
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ENUM_ENTRY(TYPE_DUP3, "operand 3") \
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ENUM_ENTRY(TYPE_DUP4, "operand 4") \
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ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state")
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#define ENUM_ENTRY(n, d) n,
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typedef enum {
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TYPES
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TYPE_max
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} OperandType;
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#undef ENUM_ENTRY
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/*
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* OperandSpecifier - The specification for how to extract and interpret one
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* operand.
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*/
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struct OperandSpecifier {
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OperandEncoding encoding;
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OperandType type;
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};
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/*
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* Indicates where the opcode modifier (if any) is to be found. Extended
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* opcodes with AddRegFrm have the opcode modifier in the ModR/M byte.
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*/
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#define MODIFIER_TYPES \
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ENUM_ENTRY(MODIFIER_NONE) \
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ENUM_ENTRY(MODIFIER_OPCODE) \
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ENUM_ENTRY(MODIFIER_MODRM)
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#define ENUM_ENTRY(n) n,
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typedef enum {
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MODIFIER_TYPES
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MODIFIER_max
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} ModifierType;
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#undef ENUM_ENTRY
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#define X86_MAX_OPERANDS 5
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/*
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* The specification for how to extract and interpret a full instruction and
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* its operands.
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*/
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struct InstructionSpecifier {
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ModifierType modifierType;
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uint8_t modifierBase;
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struct OperandSpecifier operands[X86_MAX_OPERANDS];
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/* The macro below must be defined wherever this file is included. */
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INSTRUCTION_SPECIFIER_FIELDS
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};
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/*
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* Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
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* are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
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* respectively.
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*/
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typedef enum {
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MODE_16BIT,
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MODE_32BIT,
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MODE_64BIT
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} DisassemblerMode;
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#endif
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Reference in New Issue
Block a user