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Provide Thumb2 encodings for mov's that come from MOVCC SDNodes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119744 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2010-11-18 21:46:31 +00:00
parent c884aff5f4
commit 8ee9779658
1 changed files with 13 additions and 12 deletions
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25
lib/Target/ARM/ARMInstrThumb2.td
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@ -2614,10 +2614,11 @@ defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
// FIXME: should be able to write a pattern for ARMcmov, but can't use // FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :( // a two-value operand where a dag node expects two operands. :(
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr, def t2MOVCCr : T2TwoReg<
"mov", ".w\t$dst, $true", (outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm), IIC_iCMOVr,
[/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>, "mov", ".w\t$Rd, $Rm",
RegConstraint<"$false = $dst"> { [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $Rd"> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
let Inst{24-21} = 0b0010; let Inst{24-21} = 0b0010;
@ -2628,10 +2629,10 @@ def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
} }
let isMoveImm = 1 in let isMoveImm = 1 in
def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true), def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
IIC_iCMOVi, "mov", ".w\t$dst, $true", IIC_iCMOVi, "mov", ".w\t$Rd, $imm",
[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst"> { RegConstraint<"$false = $Rd"> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 0; let Inst{25} = 0;
let Inst{24-21} = 0b0010; let Inst{24-21} = 0b0010;
@ -2667,11 +2668,11 @@ def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">; IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
let isMoveImm = 1 in let isMoveImm = 1 in
def t2MVNCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true), def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
IIC_iCMOVi, "mvn", ".w\t$dst, $true", IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm_not:$true, [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
imm:$cc, CCR:$ccr))*/]>, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst"> { RegConstraint<"$false = $Rd"> {
let Inst{31-27} = 0b11110; let Inst{31-27} = 0b11110;
let Inst{25} = 0; let Inst{25} = 0;
let Inst{24-21} = 0b0011; let Inst{24-21} = 0b0011;