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Emit a single _udivmodsi4 libcall instead of two separate _udivsi3 and
_umodsi3 libcalls if they have the same arguments. This optimization was apparently broken if one of the node was replaced in place. rdar://11714607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158900 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1930,9 +1930,11 @@ static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
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return TLI.getLibcallName(LC) != 0;
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}
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/// UseDivRem - Only issue divrem libcall if both quotient and remainder are
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/// useDivRem - Only issue divrem libcall if both quotient and remainder are
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/// needed.
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static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) {
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static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
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// The other use might have been replaced with a divrem already.
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unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
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unsigned OtherOpcode = 0;
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if (isSigned)
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OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
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@ -1946,7 +1948,7 @@ static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) {
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SDNode *User = *UI;
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if (User == Node)
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continue;
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if (User->getOpcode() == OtherOpcode &&
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if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
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User->getOperand(0) == Op0 &&
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User->getOperand(1) == Op1)
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return true;
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@ -3092,7 +3094,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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Tmp3 = Node->getOperand(1);
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if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
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(isDivRemLibcallAvailable(Node, isSigned, TLI) &&
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UseDivRem(Node, isSigned, false))) {
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useDivRem(Node, isSigned, false))) {
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Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
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} else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
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// X % Y -> X-X/Y*Y
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@ -3120,7 +3122,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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SDVTList VTs = DAG.getVTList(VT, VT);
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if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
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(isDivRemLibcallAvailable(Node, isSigned, TLI) &&
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UseDivRem(Node, isSigned, true)))
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useDivRem(Node, isSigned, true)))
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Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
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Node->getOperand(1));
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else if (isSigned)
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=arm-apple-ios5.0 | FileCheck %s
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; RUN: llc < %s -mtriple=arm-apple-ios5.0 -mcpu=cortex-a8 | FileCheck %s
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define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
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entry:
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@ -56,3 +56,17 @@ bb1:
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declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readnone
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declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind
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; rdar://11714607
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define i32 @howmany(i32 %x, i32 %y) nounwind {
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entry:
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; CHECK: howmany:
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; CHECK: bl ___udivmodsi4
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; CHECK-NOT: ___udivsi3
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%rem = urem i32 %x, %y
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%div = udiv i32 %x, %y
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%not.cmp = icmp ne i32 %rem, 0
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%add = zext i1 %not.cmp to i32
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%cond = add i32 %add, %div
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ret i32 %cond
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}
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