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Fixes a bug in vector load legalization that confused bits and bytes.

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Differential Revision: http://reviews.llvm.org/D7400

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228168 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Kuperstein
2015-02-04 18:54:01 +00:00
parent 6882095643
commit 8f260e3084
2 changed files with 74 additions and 7 deletions
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6
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@ -554,9 +554,9 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
BitOffset += SrcEltBits; BitOffset += SrcEltBits;
if (BitOffset >= WideBits) { if (BitOffset >= WideBits) {
WideIdx++; WideIdx++;
Offset -= WideBits; BitOffset -= WideBits;
if (Offset > 0) { if (BitOffset > 0) {
ShAmt = DAG.getConstant(SrcEltBits - Offset, ShAmt = DAG.getConstant(SrcEltBits - BitOffset,
TLI.getShiftAmountTy(WideVT)); TLI.getShiftAmountTy(WideVT));
Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt); Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask); Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);

75
test/CodeGen/X86/pr15267.ll
View File

@ -4,8 +4,7 @@ define <4 x i3> @test1(<4 x i3>* %in) nounwind {
%ret = load <4 x i3>* %in, align 1 %ret = load <4 x i3>* %in, align 1
ret <4 x i3> %ret ret <4 x i3> %ret
} }
; CHECK-LABEL: test1
; CHECK: test1
; CHECK: movzwl ; CHECK: movzwl
; CHECK: shrl $3 ; CHECK: shrl $3
; CHECK: andl $7 ; CHECK: andl $7
@ -25,7 +24,7 @@ define <4 x i1> @test2(<4 x i1>* %in) nounwind {
ret <4 x i1> %ret ret <4 x i1> %ret
} }
; CHECK: test2 ; CHECK-LABEL: test2
; CHECK: movzbl ; CHECK: movzbl
; CHECK: shrl ; CHECK: shrl
; CHECK: andl $1 ; CHECK: andl $1
@ -46,7 +45,7 @@ define <4 x i64> @test3(<4 x i1>* %in) nounwind {
ret <4 x i64> %sext ret <4 x i64> %sext
} }
; CHECK: test3 ; CHECK-LABEL: test3
; CHECK: movzbl ; CHECK: movzbl
; CHECK: movq ; CHECK: movq
; CHECK: shlq ; CHECK: shlq
@ -67,3 +66,71 @@ define <4 x i64> @test3(<4 x i1>* %in) nounwind {
; CHECK: vpunpcklqdq ; CHECK: vpunpcklqdq
; CHECK: vinsertf128 ; CHECK: vinsertf128
; CHECK: ret ; CHECK: ret
define <16 x i4> @test4(<16 x i4>* %in) nounwind {
%ret = load <16 x i4>* %in, align 1
ret <16 x i4> %ret
}
; CHECK-LABEL: test4
; CHECK: movl
; CHECK-NEXT: shrl
; CHECK-NEXT: andl
; CHECK-NEXT: movl
; CHECK-NEXT: andl
; CHECK-NEXT: vmovd
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movl
; CHECK-NEXT: shrl
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movl
; CHECK-NEXT: shrl
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movl
; CHECK-NEXT: shrl
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movl
; CHECK-NEXT: shrl
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movl
; CHECK-NEXT: shrl
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movl
; CHECK-NEXT: shrl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movq
; CHECK-NEXT: shrq
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movq
; CHECK-NEXT: shrq
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movq
; CHECK-NEXT: shrq
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movq
; CHECK-NEXT: shrq
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movq
; CHECK-NEXT: shrq
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movq
; CHECK-NEXT: shrq
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: movq
; CHECK-NEXT: shrq
; CHECK-NEXT: andl
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: shrq
; CHECK-NEXT: vpinsrb
; CHECK-NEXT: retq