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Fix PR1390.

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Don't spill extra register to align the stack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36814 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Lauro Ramos Venancio 2007-05-05 23:44:41 +00:00
parent 07b54242a8
commit 8f57667a5d
2 changed files with 51 additions and 38 deletions
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48
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -1131,26 +1131,6 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
NumGPRSpills++;
}
// If stack and double are 8-byte aligned and we are spilling an odd number
// of GPRs. Spill one extra callee save GPR so we won't have to pad between
// the integer and double callee save areas.
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
if (TargetAlign == 8 && (NumGPRSpills & 1)) {
if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
unsigned Reg = UnspilledCS1GPRs.front();
MF.setPhysRegUsed(Reg);
AFI->setCSRegisterIsSpilled(Reg);
if (!isReservedReg(MF, Reg))
ExtraCSSpill = true;
} else if (!UnspilledCS2GPRs.empty()) {
unsigned Reg = UnspilledCS2GPRs.front();
MF.setPhysRegUsed(Reg);
AFI->setCSRegisterIsSpilled(Reg);
if (!isReservedReg(MF, Reg))
ExtraCSSpill = true;
}
}
// Estimate if we might need to scavenge a register at some point in order
// to materialize a stack offset. If so, either spill one additiona
// callee-saved register or reserve a special spill slot to facilitate
@ -1180,29 +1160,26 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
if (Size >= Limit) {
// If any non-reserved CS register isn't spilled, just spill one or two
// extra. That should take care of it!
unsigned NumExtras = TargetAlign / 4;
SmallVector<unsigned, 2> Extras;
while (NumExtras && !UnspilledCS1GPRs.empty()) {
unsigned Extra;
while (!ExtraCSSpill && !UnspilledCS1GPRs.empty()) {
unsigned Reg = UnspilledCS1GPRs.back();
UnspilledCS1GPRs.pop_back();
if (!isReservedReg(MF, Reg)) {
Extras.push_back(Reg);
NumExtras--;
Extra = Reg;
ExtraCSSpill = true;
}
}
while (NumExtras && !UnspilledCS2GPRs.empty()) {
while (!ExtraCSSpill && !UnspilledCS2GPRs.empty()) {
unsigned Reg = UnspilledCS2GPRs.back();
UnspilledCS2GPRs.pop_back();
if (!isReservedReg(MF, Reg)) {
Extras.push_back(Reg);
NumExtras--;
Extra = Reg;
ExtraCSSpill = true;
}
}
if (Extras.size() && NumExtras == 0) {
for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
MF.setPhysRegUsed(Extras[i]);
AFI->setCSRegisterIsSpilled(Extras[i]);
}
if (ExtraCSSpill) {
MF.setPhysRegUsed(Extra);
AFI->setCSRegisterIsSpilled(Extra);
} else {
// Reserve a slot closest to SP or frame pointer.
const TargetRegisterClass *RC = &ARM::GPRRegClass;
@ -1263,7 +1240,6 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
bool isThumb = AFI->isThumbFunction();
unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
unsigned NumBytes = MFI->getStackSize();
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
@ -1330,10 +1306,6 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
}
}
if (Align == 8 && (GPRCS1Size & 7) != 0)
// Pad CS1 to ensure proper alignment.
GPRCS1Size += 4;
if (!isThumb) {
// Build the new SUBri to adjust SP for integer callee-save spill area 1.
emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII);

41
test/CodeGen/ARM/2007-05-05-InvalidPushPop.ll Normal file
View File

@ -0,0 +1,41 @@
; RUN: llvm-as < %s | llc | not grep r11
target triple = "thumb-linux-gnueabi"
%struct.__sched_param = type { i32 }
%struct.pthread_attr_t = type { i32, i32, %struct.__sched_param, i32, i32, i32, i32, i8*, i32 }
@i.1882 = internal global i32 1 ; <i32*> [#uses=2]
@.str = internal constant [14 x i8] c"Thread 1: %d\0A\00" ; <[14 x i8]*> [#uses=1]
@.str1 = internal constant [14 x i8] c"Thread 2: %d\0A\00" ; <[14 x i8]*> [#uses=1]
define i8* @f(i8* %a) {
entry:
%tmp1 = load i32* @i.1882 ; <i32> [#uses=1]
%tmp2 = add i32 %tmp1, 1 ; <i32> [#uses=2]
store i32 %tmp2, i32* @i.1882
%tmp34 = inttoptr i32 %tmp2 to i8* ; <i8*> [#uses=1]
ret i8* %tmp34
}
define i32 @main() {
entry:
%t = alloca i32, align 4 ; <i32*> [#uses=4]
%ret = alloca i32, align 4 ; <i32*> [#uses=3]
%tmp1 = call i32 @pthread_create( i32* %t, %struct.pthread_attr_t* null, i8* (i8*)* @f, i8* null ) ; <i32> [#uses=0]
%tmp2 = load i32* %t ; <i32> [#uses=1]
%ret3 = bitcast i32* %ret to i8** ; <i8**> [#uses=2]
%tmp4 = call i32 @pthread_join( i32 %tmp2, i8** %ret3 ) ; <i32> [#uses=0]
%tmp5 = load i32* %ret ; <i32> [#uses=1]
%tmp7 = call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @.str, i32 0, i32 0), i32 %tmp5 ) ; <i32> [#uses=0]
%tmp8 = call i32 @pthread_create( i32* %t, %struct.pthread_attr_t* null, i8* (i8*)* @f, i8* null ) ; <i32> [#uses=0]
%tmp9 = load i32* %t ; <i32> [#uses=1]
%tmp11 = call i32 @pthread_join( i32 %tmp9, i8** %ret3 ) ; <i32> [#uses=0]
%tmp12 = load i32* %ret ; <i32> [#uses=1]
%tmp14 = call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @.str1, i32 0, i32 0), i32 %tmp12 ) ; <i32> [#uses=0]
ret i32 0
}
declare i32 @pthread_create(i32*, %struct.pthread_attr_t*, i8* (i8*)*, i8*)
declare i32 @pthread_join(i32, i8**)
declare i32 @printf(i8*, ...)