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Fix PR1390.
Don't spill extra register to align the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36814 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1131,26 +1131,6 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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NumGPRSpills++;
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}
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// If stack and double are 8-byte aligned and we are spilling an odd number
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// of GPRs. Spill one extra callee save GPR so we won't have to pad between
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// the integer and double callee save areas.
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unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
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if (TargetAlign == 8 && (NumGPRSpills & 1)) {
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if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
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unsigned Reg = UnspilledCS1GPRs.front();
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MF.setPhysRegUsed(Reg);
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AFI->setCSRegisterIsSpilled(Reg);
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if (!isReservedReg(MF, Reg))
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ExtraCSSpill = true;
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} else if (!UnspilledCS2GPRs.empty()) {
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unsigned Reg = UnspilledCS2GPRs.front();
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MF.setPhysRegUsed(Reg);
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AFI->setCSRegisterIsSpilled(Reg);
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if (!isReservedReg(MF, Reg))
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ExtraCSSpill = true;
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}
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}
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// Estimate if we might need to scavenge a register at some point in order
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// to materialize a stack offset. If so, either spill one additiona
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// callee-saved register or reserve a special spill slot to facilitate
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@ -1180,29 +1160,26 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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if (Size >= Limit) {
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// If any non-reserved CS register isn't spilled, just spill one or two
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// extra. That should take care of it!
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unsigned NumExtras = TargetAlign / 4;
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SmallVector<unsigned, 2> Extras;
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while (NumExtras && !UnspilledCS1GPRs.empty()) {
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unsigned Extra;
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while (!ExtraCSSpill && !UnspilledCS1GPRs.empty()) {
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unsigned Reg = UnspilledCS1GPRs.back();
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UnspilledCS1GPRs.pop_back();
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if (!isReservedReg(MF, Reg)) {
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Extras.push_back(Reg);
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NumExtras--;
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Extra = Reg;
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ExtraCSSpill = true;
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}
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}
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while (NumExtras && !UnspilledCS2GPRs.empty()) {
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while (!ExtraCSSpill && !UnspilledCS2GPRs.empty()) {
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unsigned Reg = UnspilledCS2GPRs.back();
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UnspilledCS2GPRs.pop_back();
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if (!isReservedReg(MF, Reg)) {
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Extras.push_back(Reg);
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NumExtras--;
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Extra = Reg;
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ExtraCSSpill = true;
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}
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}
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if (Extras.size() && NumExtras == 0) {
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for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
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MF.setPhysRegUsed(Extras[i]);
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AFI->setCSRegisterIsSpilled(Extras[i]);
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}
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if (ExtraCSSpill) {
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MF.setPhysRegUsed(Extra);
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AFI->setCSRegisterIsSpilled(Extra);
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} else {
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// Reserve a slot closest to SP or frame pointer.
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const TargetRegisterClass *RC = &ARM::GPRRegClass;
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@ -1263,7 +1240,6 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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bool isThumb = AFI->isThumbFunction();
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unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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unsigned NumBytes = MFI->getStackSize();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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@ -1330,10 +1306,6 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
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}
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}
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if (Align == 8 && (GPRCS1Size & 7) != 0)
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// Pad CS1 to ensure proper alignment.
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GPRCS1Size += 4;
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if (!isThumb) {
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// Build the new SUBri to adjust SP for integer callee-save spill area 1.
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emitSPUpdate(MBB, MBBI, -GPRCS1Size, isThumb, TII);
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41
test/CodeGen/ARM/2007-05-05-InvalidPushPop.ll
Normal file
41
test/CodeGen/ARM/2007-05-05-InvalidPushPop.ll
Normal file
@ -0,0 +1,41 @@
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; RUN: llvm-as < %s | llc | not grep r11
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target triple = "thumb-linux-gnueabi"
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%struct.__sched_param = type { i32 }
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%struct.pthread_attr_t = type { i32, i32, %struct.__sched_param, i32, i32, i32, i32, i8*, i32 }
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@i.1882 = internal global i32 1 ; <i32*> [#uses=2]
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@.str = internal constant [14 x i8] c"Thread 1: %d\0A\00" ; <[14 x i8]*> [#uses=1]
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@.str1 = internal constant [14 x i8] c"Thread 2: %d\0A\00" ; <[14 x i8]*> [#uses=1]
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define i8* @f(i8* %a) {
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entry:
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%tmp1 = load i32* @i.1882 ; <i32> [#uses=1]
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%tmp2 = add i32 %tmp1, 1 ; <i32> [#uses=2]
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store i32 %tmp2, i32* @i.1882
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%tmp34 = inttoptr i32 %tmp2 to i8* ; <i8*> [#uses=1]
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ret i8* %tmp34
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}
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define i32 @main() {
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entry:
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%t = alloca i32, align 4 ; <i32*> [#uses=4]
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%ret = alloca i32, align 4 ; <i32*> [#uses=3]
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%tmp1 = call i32 @pthread_create( i32* %t, %struct.pthread_attr_t* null, i8* (i8*)* @f, i8* null ) ; <i32> [#uses=0]
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%tmp2 = load i32* %t ; <i32> [#uses=1]
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%ret3 = bitcast i32* %ret to i8** ; <i8**> [#uses=2]
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%tmp4 = call i32 @pthread_join( i32 %tmp2, i8** %ret3 ) ; <i32> [#uses=0]
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%tmp5 = load i32* %ret ; <i32> [#uses=1]
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%tmp7 = call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @.str, i32 0, i32 0), i32 %tmp5 ) ; <i32> [#uses=0]
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%tmp8 = call i32 @pthread_create( i32* %t, %struct.pthread_attr_t* null, i8* (i8*)* @f, i8* null ) ; <i32> [#uses=0]
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%tmp9 = load i32* %t ; <i32> [#uses=1]
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%tmp11 = call i32 @pthread_join( i32 %tmp9, i8** %ret3 ) ; <i32> [#uses=0]
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%tmp12 = load i32* %ret ; <i32> [#uses=1]
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%tmp14 = call i32 (i8*, ...)* @printf( i8* getelementptr ([14 x i8]* @.str1, i32 0, i32 0), i32 %tmp12 ) ; <i32> [#uses=0]
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ret i32 0
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}
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declare i32 @pthread_create(i32*, %struct.pthread_attr_t*, i8* (i8*)*, i8*)
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declare i32 @pthread_join(i32, i8**)
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declare i32 @printf(i8*, ...)
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