From 8f777a205e4523b773ba3af3bad007d93da56a9a Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Wed, 15 Sep 2010 04:08:38 +0000
Subject: [PATCH] add some aliases for f[u]comi, part of rdar://8431422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113930 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/AsmParser/X86AsmParser.cpp | 16 +++++++++-------
 test/MC/AsmParser/X86/x86_instructions.s  | 14 ++++++++++++++
 2 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index dde34631ef4..c21fc7ab56e 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -933,13 +933,15 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
                                              NameLoc, NameLoc));
   }
   
-  // The assembler accepts these instructions with no operand as a synonym for
-  // an instruction acting on st,st(1).  e.g. "faddp" -> "faddp %st(0),%st(1)".
-  //if (() &&
-  //    Operands.size() == 1) {
-  //  Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
-  //                                           NameLoc, NameLoc));
-  //}
+  // The assembler accepts these instructions with two few operands as a synonym
+  // for taking %st(1),%st(0) or X, %st(0).
+  if ((Name == "fcomi" || Name == "fucomi") && Operands.size() < 3) {
+    if (Operands.size() == 1)
+      Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
+                                               NameLoc, NameLoc));
+    Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
+                                             NameLoc, NameLoc));
+  }
   
   return false;
 }
diff --git a/test/MC/AsmParser/X86/x86_instructions.s b/test/MC/AsmParser/X86/x86_instructions.s
index 4bdd171445d..cd7c6e117a7 100644
--- a/test/MC/AsmParser/X86/x86_instructions.s
+++ b/test/MC/AsmParser/X86/x86_instructions.s
@@ -235,3 +235,17 @@ fsubrp
 fmulp
 fdivp
 fdivrp
+
+// CHECK: fcomi	%st(1), %st(0)
+// CHECK: fcomi	%st(2), %st(0)
+// CHECK: fucomi	%st(1), %st(0)
+// CHECK: fucomi	%st(2), %st(0)
+// CHECK: fucomi	%st(2), %st(0)
+
+fcomi
+fcomi	%st(2)
+fucomi
+fucomi	%st(2)
+fucomi	%st(2), %st
+
+