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Constrain PowerPC autovectorization to fix bug 15041.

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Certain vector operations don't vectorize well with the current
PowerPC implementation.  Element insert/extract performs poorly
without VSX support because Altivec requires going through memory.
SREM, UREM, and VSELECT all produce bad scalar code.

There's a lot of work to do for the cost model before
autovectorization will be tuned well, and this is not an attempt to
address the larger problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174660 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt 2013-02-07 20:33:57 +00:00
parent 0c66403efd
commit 8f7dc823bf
1 changed files with 19 additions and 0 deletions
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19
lib/Target/PowerPC/PPCTargetTransformInfo.cpp
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@ -194,6 +194,25 @@ unsigned PPCTTI::getVectorInstrCost(unsigned Opcode, Type *Val,
unsigned Index) const {
assert(Val->isVectorTy() && "This must be a vector type");
const unsigned Awful = 1000;
// Vector element insert/extract with Altivec is very expensive.
// Until VSX is available, avoid vectorizing loops that require
// these operations.
if (Opcode == ISD::EXTRACT_VECTOR_ELT ||
Opcode == ISD::INSERT_VECTOR_ELT)
return Awful;
// We don't vectorize SREM/UREM so well. Constrain the vectorizer
// for those as well.
if (Opcode == ISD::SREM || Opcode == ISD::UREM)
return Awful;
// VSELECT is not yet implemented, leading to use of insert/extract
// and ISEL, hence not a good idea.
if (Opcode == ISD::VSELECT)
return Awful;
return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
}