mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2026-04-26 12:20:42 +00:00
Added support for ARM disassembly to edis.
I also added a rule to the ARM target's Makefile to build the ARM-specific instruction information table for the enhanced disassembler. I will add the test harness for all this stuff in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Callanan
+410
-169
@@ -23,10 +23,11 @@
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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#include <vector>
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#include <map>
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#include <string>
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#include <vector>
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#define MAX_OPERANDS 5
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#define MAX_OPERANDS 13
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#define MAX_SYNTAXES 2
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using namespace llvm;
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@@ -54,9 +55,9 @@ namespace {
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unsigned int index = 0;
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unsigned int numEntries = Entries.size();
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for(index = 0; index < numEntries; ++index) {
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for (index = 0; index < numEntries; ++index) {
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o.indent(i) << Entries[index];
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if(index < (numEntries - 1))
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if (index < (numEntries - 1))
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o << ",";
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o << "\n";
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}
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@@ -88,24 +89,24 @@ namespace {
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class StructEmitter {
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private:
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std::string Name;
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std::vector<std::string> MemberTypes;
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std::vector<std::string> MemberNames;
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typedef std::pair<const char*, const char*> member;
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std::vector< member > Members;
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public:
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StructEmitter(const char *N) : Name(N) {
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}
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void addMember(const char *t, const char *n) {
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MemberTypes.push_back(std::string(t));
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MemberNames.push_back(std::string(n));
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member m(t, n);
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Members.push_back(m);
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}
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void emit(raw_ostream &o, unsigned int &i) {
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o.indent(i) << "struct " << Name.c_str() << " {" << "\n";
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i += 2;
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unsigned int index = 0;
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unsigned int numMembers = MemberTypes.size();
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unsigned int numMembers = Members.size();
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for (index = 0; index < numMembers; ++index) {
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o.indent(i) << MemberTypes[index] << " " << MemberNames[index] << ";";
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o << "\n";
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o.indent(i) << Members[index].first << " ";
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o.indent(i) << Members[index].second << ";" << "\n";
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}
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i -= 2;
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@@ -121,47 +122,87 @@ namespace {
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class LiteralConstantEmitter : public ConstantEmitter {
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private:
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std::string Literal;
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bool IsNumber;
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union {
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int Number;
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const char* String;
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};
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public:
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LiteralConstantEmitter(const char *literal) : Literal(literal) {
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LiteralConstantEmitter(const char *string) :
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IsNumber(false),
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String(string) {
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}
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LiteralConstantEmitter(int literal) {
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char buf[256];
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snprintf(buf, 256, "%d", literal);
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Literal = buf;
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LiteralConstantEmitter(int number = 0) :
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IsNumber(true),
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Number(number) {
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}
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void set(const char *string) {
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IsNumber = false;
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Number = 0;
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String = string;
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}
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void set(int number) {
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IsNumber = true;
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String = NULL;
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Number = number;
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}
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bool is(const char *string) {
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return !strcmp(String, string);
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}
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void emit(raw_ostream &o, unsigned int &i) {
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o << Literal;
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if (IsNumber)
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o << Number;
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else
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o << String;
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}
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};
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class CompoundConstantEmitter : public ConstantEmitter {
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private:
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std::vector<ConstantEmitter*> Entries;
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unsigned int Padding;
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std::vector<ConstantEmitter *> Entries;
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public:
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CompoundConstantEmitter() {
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}
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~CompoundConstantEmitter() {
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unsigned int index;
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unsigned int numEntries = Entries.size();
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for (index = 0; index < numEntries; ++index) {
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delete Entries[index];
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}
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CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
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}
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CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
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Entries.push_back(e);
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return *this;
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}
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~CompoundConstantEmitter() {
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while (Entries.size()) {
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ConstantEmitter *entry = Entries.back();
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Entries.pop_back();
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delete entry;
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}
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}
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void emit(raw_ostream &o, unsigned int &i) {
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o << "{" << "\n";
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i += 2;
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unsigned int index;
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unsigned int numEntries = Entries.size();
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for (index = 0; index < numEntries; ++index) {
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unsigned int numToPrint;
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if (Padding) {
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if (numEntries > Padding) {
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fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
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llvm_unreachable("More entries than padding");
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}
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numToPrint = Padding;
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} else {
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numToPrint = numEntries;
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}
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for (index = 0; index < numToPrint; ++index) {
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o.indent(i);
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Entries[index]->emit(o, i);
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if (index < (numEntries - 1))
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if (index < numEntries)
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Entries[index]->emit(o, i);
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else
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o << "-1";
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if (index < (numToPrint - 1))
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o << ",";
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o << "\n";
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}
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@@ -226,40 +267,31 @@ void populateOperandOrder(CompoundConstantEmitter *operandOrder,
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++operandIterator) {
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if (operandIterator->OperandType ==
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AsmWriterOperand::isMachineInstrOperand) {
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char buf[2];
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snprintf(buf, sizeof(buf), "%u", operandIterator->CGIOpNo);
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operandOrder->addEntry(new LiteralConstantEmitter(buf));
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operandOrder->addEntry(
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new LiteralConstantEmitter(operandIterator->CGIOpNo));
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numArgs++;
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}
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}
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for(; numArgs < MAX_OPERANDS; numArgs++) {
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operandOrder->addEntry(new LiteralConstantEmitter("-1"));
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}
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}
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/////////////////////////////////////////////////////
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// Support functions for handling X86 instructions //
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/////////////////////////////////////////////////////
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#define ADDFLAG(flag) flags->addEntry(flag)
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#define SET(flag) { type->set(flag); return 0; }
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#define REG(str) if (name == str) { ADDFLAG("kOperandFlagRegister"); return 0; }
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#define MEM(str) if (name == str) { ADDFLAG("kOperandFlagMemory"); return 0; }
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#define LEA(str) if (name == str) { ADDFLAG("kOperandFlagEffectiveAddress"); \
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return 0; }
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#define IMM(str) if (name == str) { ADDFLAG("kOperandFlagImmediate"); \
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return 0; }
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#define PCR(str) if (name == str) { ADDFLAG("kOperandFlagMemory"); \
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ADDFLAG("kOperandFlagPCRelative"); \
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return 0; }
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#define REG(str) if (name == str) SET("kOperandTypeRegister");
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#define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
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#define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
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#define IMM(str) if (name == str) SET("kOperandTypeImmediate");
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#define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
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/// X86FlagFromOpName - Processes the name of a single X86 operand (which is
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/// actually its type) and translates it into an operand flag
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/// X86TypeFromOpName - Processes the name of a single X86 operand (which is
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/// actually its type) and translates it into an operand type
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///
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/// @arg flags - The flags object to add the flag to
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/// @arg flags - The type object to set
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/// @arg name - The name of the operand
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static int X86FlagFromOpName(FlagsConstantEmitter *flags,
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static int X86TypeFromOpName(LiteralConstantEmitter *type,
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const std::string &name) {
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REG("GR8");
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REG("GR8_NOREX");
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@@ -282,6 +314,19 @@ static int X86FlagFromOpName(FlagsConstantEmitter *flags,
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REG("CONTROL_REG_32");
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REG("CONTROL_REG_64");
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IMM("i8imm");
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IMM("i16imm");
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IMM("i16i8imm");
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IMM("i32imm");
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IMM("i32imm_pcrel");
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IMM("i32i8imm");
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IMM("i64imm");
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IMM("i64i8imm");
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IMM("i64i32imm");
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IMM("i64i32imm_pcrel");
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IMM("SSECC");
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// all R, I, R, I, R
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MEM("i8mem");
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MEM("i8mem_NOREX");
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MEM("i16mem");
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@@ -301,22 +346,12 @@ static int X86FlagFromOpName(FlagsConstantEmitter *flags,
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MEM("f128mem");
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MEM("opaque512mem");
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// all R, I, R, I
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LEA("lea32mem");
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LEA("lea64_32mem");
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LEA("lea64mem");
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IMM("i8imm");
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IMM("i16imm");
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IMM("i16i8imm");
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IMM("i32imm");
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IMM("i32imm_pcrel");
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IMM("i32i8imm");
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IMM("i64imm");
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IMM("i64i8imm");
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IMM("i64i32imm");
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IMM("i64i32imm_pcrel");
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IMM("SSECC");
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// all I
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PCR("brtarget8");
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PCR("offset8");
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PCR("offset16");
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@@ -332,7 +367,8 @@ static int X86FlagFromOpName(FlagsConstantEmitter *flags,
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#undef LEA
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#undef IMM
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#undef PCR
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#undef ADDFLAG
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#undef SET
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/// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
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/// the appropriate flags to their descriptors
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@@ -340,7 +376,7 @@ static int X86FlagFromOpName(FlagsConstantEmitter *flags,
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/// @operandFlags - A reference the array of operand flag objects
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/// @inst - The instruction to use as a source of information
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static void X86PopulateOperands(
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FlagsConstantEmitter *(&operandFlags)[MAX_OPERANDS],
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LiteralConstantEmitter *(&operandTypes)[MAX_OPERANDS],
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const CodeGenInstruction &inst) {
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if (!inst.TheDef->isSubClassOf("X86Inst"))
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return;
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@@ -353,7 +389,7 @@ static void X86PopulateOperands(
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inst.OperandList[index];
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Record &rec = *operandInfo.Rec;
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if (X86FlagFromOpName(operandFlags[index], rec.getName())) {
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if (X86TypeFromOpName(operandTypes[index], rec.getName())) {
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errs() << "Operand type: " << rec.getName().c_str() << "\n";
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errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
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errs() << "Instruction mame: " << inst.TheDef->getName().c_str() << "\n";
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@@ -369,10 +405,11 @@ static void X86PopulateOperands(
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/// between names and operand indices
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/// @opName - The name of the operand
|
||||
/// @flag - The name of the flag to add
|
||||
static inline void decorate1(FlagsConstantEmitter *(&operandFlags)[MAX_OPERANDS],
|
||||
const CodeGenInstruction &inst,
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||||
const char *opName,
|
||||
const char *opFlag) {
|
||||
static inline void decorate1(
|
||||
FlagsConstantEmitter *(&operandFlags)[MAX_OPERANDS],
|
||||
const CodeGenInstruction &inst,
|
||||
const char *opName,
|
||||
const char *opFlag) {
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||||
unsigned opIndex;
|
||||
|
||||
opIndex = inst.getOperandNamed(std::string(opName));
|
||||
@@ -382,78 +419,70 @@ static inline void decorate1(FlagsConstantEmitter *(&operandFlags)[MAX_OPERANDS]
|
||||
|
||||
#define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
|
||||
|
||||
#define MOV(source, target) { \
|
||||
instFlags.addEntry("kInstructionFlagMove"); \
|
||||
DECORATE1(source, "kOperandFlagSource"); \
|
||||
DECORATE1(target, "kOperandFlagTarget"); \
|
||||
#define MOV(source, target) { \
|
||||
instType.set("kInstructionTypeMove"); \
|
||||
DECORATE1(source, "kOperandFlagSource"); \
|
||||
DECORATE1(target, "kOperandFlagTarget"); \
|
||||
}
|
||||
|
||||
#define BRANCH(target) { \
|
||||
instFlags.addEntry("kInstructionFlagBranch"); \
|
||||
DECORATE1(target, "kOperandFlagTarget"); \
|
||||
#define BRANCH(target) { \
|
||||
instType.set("kInstructionTypeBranch"); \
|
||||
DECORATE1(target, "kOperandFlagTarget"); \
|
||||
}
|
||||
|
||||
#define PUSH(source) { \
|
||||
instFlags.addEntry("kInstructionFlagPush"); \
|
||||
DECORATE1(source, "kOperandFlagSource"); \
|
||||
#define PUSH(source) { \
|
||||
instType.set("kInstructionTypePush"); \
|
||||
DECORATE1(source, "kOperandFlagSource"); \
|
||||
}
|
||||
|
||||
#define POP(target) { \
|
||||
instFlags.addEntry("kInstructionFlagPop"); \
|
||||
DECORATE1(target, "kOperandFlagTarget"); \
|
||||
#define POP(target) { \
|
||||
instType.set("kInstructionTypePop"); \
|
||||
DECORATE1(target, "kOperandFlagTarget"); \
|
||||
}
|
||||
|
||||
#define CALL(target) { \
|
||||
instFlags.addEntry("kInstructionFlagCall"); \
|
||||
DECORATE1(target, "kOperandFlagTarget"); \
|
||||
#define CALL(target) { \
|
||||
instType.set("kInstructionTypeCall"); \
|
||||
DECORATE1(target, "kOperandFlagTarget"); \
|
||||
}
|
||||
|
||||
#define RETURN() { \
|
||||
instFlags.addEntry("kInstructionFlagReturn"); \
|
||||
#define RETURN() { \
|
||||
instType.set("kInstructionTypeReturn"); \
|
||||
}
|
||||
|
||||
/// X86ExtractSemantics - Performs various checks on the name of an X86
|
||||
/// instruction to determine what sort of an instruction it is and then adds
|
||||
/// the appropriate flags to the instruction and its operands
|
||||
///
|
||||
/// @arg instFlags - A reference to the flags for the instruction as a whole
|
||||
/// @arg instType - A reference to the type for the instruction as a whole
|
||||
/// @arg operandFlags - A reference to the array of operand flag object pointers
|
||||
/// @arg inst - A reference to the original instruction
|
||||
static void X86ExtractSemantics(FlagsConstantEmitter &instFlags,
|
||||
FlagsConstantEmitter *(&operandFlags)[MAX_OPERANDS],
|
||||
const CodeGenInstruction &inst) {
|
||||
static void X86ExtractSemantics(
|
||||
LiteralConstantEmitter &instType,
|
||||
FlagsConstantEmitter *(&operandFlags)[MAX_OPERANDS],
|
||||
const CodeGenInstruction &inst) {
|
||||
const std::string &name = inst.TheDef->getName();
|
||||
|
||||
if (name.find("MOV") != name.npos) {
|
||||
if (name.find("MOV_V") != name.npos) {
|
||||
// ignore (this is a pseudoinstruction)
|
||||
}
|
||||
else if (name.find("MASK") != name.npos) {
|
||||
} else if (name.find("MASK") != name.npos) {
|
||||
// ignore (this is a masking move)
|
||||
}
|
||||
else if (name.find("r0") != name.npos) {
|
||||
} else if (name.find("r0") != name.npos) {
|
||||
// ignore (this is a pseudoinstruction)
|
||||
}
|
||||
else if (name.find("PS") != name.npos ||
|
||||
} else if (name.find("PS") != name.npos ||
|
||||
name.find("PD") != name.npos) {
|
||||
// ignore (this is a shuffling move)
|
||||
}
|
||||
else if (name.find("MOVS") != name.npos) {
|
||||
} else if (name.find("MOVS") != name.npos) {
|
||||
// ignore (this is a string move)
|
||||
}
|
||||
else if (name.find("_F") != name.npos) {
|
||||
} else if (name.find("_F") != name.npos) {
|
||||
// TODO handle _F moves to ST(0)
|
||||
}
|
||||
else if (name.find("a") != name.npos) {
|
||||
} else if (name.find("a") != name.npos) {
|
||||
// TODO handle moves to/from %ax
|
||||
}
|
||||
else if (name.find("CMOV") != name.npos) {
|
||||
} else if (name.find("CMOV") != name.npos) {
|
||||
MOV("src2", "dst");
|
||||
}
|
||||
else if (name.find("PC") != name.npos) {
|
||||
} else if (name.find("PC") != name.npos) {
|
||||
MOV("label", "reg")
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
MOV("src", "dst");
|
||||
}
|
||||
}
|
||||
@@ -462,8 +491,7 @@ static void X86ExtractSemantics(FlagsConstantEmitter &instFlags,
|
||||
name.find("J") == 0) {
|
||||
if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
|
||||
BRANCH("off");
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
BRANCH("dst");
|
||||
}
|
||||
}
|
||||
@@ -471,19 +499,15 @@ static void X86ExtractSemantics(FlagsConstantEmitter &instFlags,
|
||||
if (name.find("PUSH") != name.npos) {
|
||||
if (name.find("FS") != name.npos ||
|
||||
name.find("GS") != name.npos) {
|
||||
instFlags.addEntry("kInstructionFlagPush");
|
||||
instType.set("kInstructionTypePush");
|
||||
// TODO add support for fixed operands
|
||||
}
|
||||
else if (name.find("F") != name.npos) {
|
||||
} else if (name.find("F") != name.npos) {
|
||||
// ignore (this pushes onto the FP stack)
|
||||
}
|
||||
else if (name[name.length() - 1] == 'm') {
|
||||
} else if (name[name.length() - 1] == 'm') {
|
||||
PUSH("src");
|
||||
}
|
||||
else if (name.find("i") != name.npos) {
|
||||
} else if (name.find("i") != name.npos) {
|
||||
PUSH("imm");
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
PUSH("reg");
|
||||
}
|
||||
}
|
||||
@@ -491,19 +515,15 @@ static void X86ExtractSemantics(FlagsConstantEmitter &instFlags,
|
||||
if (name.find("POP") != name.npos) {
|
||||
if (name.find("POPCNT") != name.npos) {
|
||||
// ignore (not a real pop)
|
||||
}
|
||||
else if (name.find("FS") != name.npos ||
|
||||
} else if (name.find("FS") != name.npos ||
|
||||
name.find("GS") != name.npos) {
|
||||
instFlags.addEntry("kInstructionFlagPop");
|
||||
instType.set("kInstructionTypePop");
|
||||
// TODO add support for fixed operands
|
||||
}
|
||||
else if (name.find("F") != name.npos) {
|
||||
} else if (name.find("F") != name.npos) {
|
||||
// ignore (this pops from the FP stack)
|
||||
}
|
||||
else if (name[name.length() - 1] == 'm') {
|
||||
} else if (name[name.length() - 1] == 'm') {
|
||||
POP("dst");
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
POP("reg");
|
||||
}
|
||||
}
|
||||
@@ -511,17 +531,13 @@ static void X86ExtractSemantics(FlagsConstantEmitter &instFlags,
|
||||
if (name.find("CALL") != name.npos) {
|
||||
if (name.find("ADJ") != name.npos) {
|
||||
// ignore (not a call)
|
||||
}
|
||||
else if (name.find("SYSCALL") != name.npos) {
|
||||
} else if (name.find("SYSCALL") != name.npos) {
|
||||
// ignore (doesn't go anywhere we know about)
|
||||
}
|
||||
else if (name.find("VMCALL") != name.npos) {
|
||||
} else if (name.find("VMCALL") != name.npos) {
|
||||
// ignore (rather different semantics than a regular call)
|
||||
}
|
||||
else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
|
||||
} else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
|
||||
CALL("off");
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
CALL("dst");
|
||||
}
|
||||
}
|
||||
@@ -538,9 +554,182 @@ static void X86ExtractSemantics(FlagsConstantEmitter &instFlags,
|
||||
#undef CALL
|
||||
#undef RETURN
|
||||
|
||||
#undef COND_DECORATE_2
|
||||
#undef COND_DECORATE_1
|
||||
#undef DECORATE1
|
||||
/////////////////////////////////////////////////////
|
||||
// Support functions for handling ARM instructions //
|
||||
/////////////////////////////////////////////////////
|
||||
|
||||
#define SET(flag) { type->set(flag); return 0; }
|
||||
|
||||
#define REG(str) if (name == str) SET("kOperandTypeRegister");
|
||||
#define IMM(str) if (name == str) SET("kOperandTypeImmediate");
|
||||
|
||||
#define MISC(str, type) if (name == str) SET(type);
|
||||
|
||||
/// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
|
||||
/// actually its type) and translates it into an operand type
|
||||
///
|
||||
/// @arg type - The type object to set
|
||||
/// @arg name - The name of the operand
|
||||
static int ARMFlagFromOpName(LiteralConstantEmitter *type,
|
||||
const std::string &name) {
|
||||
REG("GPR");
|
||||
REG("cc_out");
|
||||
REG("s_cc_out");
|
||||
REG("tGPR");
|
||||
REG("DPR");
|
||||
REG("SPR");
|
||||
REG("QPR");
|
||||
REG("DPR_VFP2");
|
||||
REG("DPR_8");
|
||||
|
||||
IMM("i32imm");
|
||||
IMM("bf_inv_mask_imm");
|
||||
IMM("jtblock_operand");
|
||||
IMM("nohash_imm");
|
||||
IMM("cpinst_operand");
|
||||
IMM("cps_opt");
|
||||
IMM("vfp_f64imm");
|
||||
IMM("vfp_f32imm");
|
||||
IMM("msr_mask");
|
||||
IMM("neg_zero");
|
||||
IMM("imm0_31");
|
||||
IMM("h8imm");
|
||||
IMM("h16imm");
|
||||
IMM("h32imm");
|
||||
IMM("h64imm");
|
||||
IMM("imm0_4095");
|
||||
IMM("jt2block_operand");
|
||||
IMM("t_imm_s4");
|
||||
IMM("pclabel");
|
||||
|
||||
MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
|
||||
MISC("so_reg", "kOperandTypeARMSoReg"); // R, R, I
|
||||
MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I
|
||||
MISC("so_imm", "kOperandTypeARMSoImm"); // I
|
||||
MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I
|
||||
MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I
|
||||
MISC("pred", "kOperandTypeARMPredicate"); // I, R
|
||||
MISC("it_pred", "kOperandTypeARMPredicate"); // I
|
||||
MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I
|
||||
MISC("am2offset", "kOperandTypeARMAddrMode2Offset"); // R, I
|
||||
MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I
|
||||
MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I
|
||||
MISC("addrmode4", "kOperandTypeARMAddrMode4"); // R, I
|
||||
MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I
|
||||
MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I
|
||||
MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I
|
||||
MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
|
||||
MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
|
||||
MISC("it_mask", "kOperandTypeThumbITMask"); // I
|
||||
MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
|
||||
MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
|
||||
MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
|
||||
MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
|
||||
MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
|
||||
MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
|
||||
// R, I
|
||||
MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I
|
||||
MISC("t_addrmode_s1", "kOperandTypeThumbAddrModeS1"); // R, I, R
|
||||
MISC("t_addrmode_s2", "kOperandTypeThumbAddrModeS2"); // R, I, R
|
||||
MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4"); // R, I, R
|
||||
MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
|
||||
MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#undef SOREG
|
||||
#undef SOIMM
|
||||
#undef PRED
|
||||
#undef REG
|
||||
#undef MEM
|
||||
#undef LEA
|
||||
#undef IMM
|
||||
#undef PCR
|
||||
|
||||
#undef SET
|
||||
|
||||
/// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
|
||||
/// the appropriate flags to their descriptors
|
||||
///
|
||||
/// @operandFlags - A reference the array of operand flag objects
|
||||
/// @inst - The instruction to use as a source of information
|
||||
static void ARMPopulateOperands(
|
||||
LiteralConstantEmitter *(&operandTypes)[MAX_OPERANDS],
|
||||
const CodeGenInstruction &inst) {
|
||||
if (!inst.TheDef->isSubClassOf("InstARM") &&
|
||||
!inst.TheDef->isSubClassOf("InstThumb"))
|
||||
return;
|
||||
|
||||
unsigned int index;
|
||||
unsigned int numOperands = inst.OperandList.size();
|
||||
|
||||
if (numOperands > MAX_OPERANDS) {
|
||||
fprintf(stderr, "numOperands == %llu > %llu\n",
|
||||
(uint64_t)numOperands, (uint64_t)MAX_OPERANDS);
|
||||
llvm_unreachable("Too many operands");
|
||||
}
|
||||
|
||||
for (index = 0; index < numOperands; ++index) {
|
||||
const CodeGenInstruction::OperandInfo &operandInfo =
|
||||
inst.OperandList[index];
|
||||
Record &rec = *operandInfo.Rec;
|
||||
|
||||
if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
|
||||
errs() << "Operand type: " << rec.getName().c_str() << "\n";
|
||||
errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
|
||||
errs() << "Instruction mame: " << inst.TheDef->getName().c_str() << "\n";
|
||||
llvm_unreachable("Unhandled type");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define BRANCH(target) { \
|
||||
instType.set("kInstructionTypeBranch"); \
|
||||
DECORATE1(target, "kOperandFlagTarget"); \
|
||||
}
|
||||
|
||||
/// ARMExtractSemantics - Performs various checks on the name of an ARM
|
||||
/// instruction to determine what sort of an instruction it is and then adds
|
||||
/// the appropriate flags to the instruction and its operands
|
||||
///
|
||||
/// @arg instType - A reference to the type for the instruction as a whole
|
||||
/// @arg operandTypes - A reference to the array of operand type object pointers
|
||||
/// @arg operandFlags - A reference to the array of operand flag object pointers
|
||||
/// @arg inst - A reference to the original instruction
|
||||
static void ARMExtractSemantics(
|
||||
LiteralConstantEmitter &instType,
|
||||
LiteralConstantEmitter *(&operandTypes)[MAX_OPERANDS],
|
||||
FlagsConstantEmitter *(&operandFlags)[MAX_OPERANDS],
|
||||
const CodeGenInstruction &inst) {
|
||||
const std::string &name = inst.TheDef->getName();
|
||||
|
||||
if (name == "tBcc" ||
|
||||
name == "tB" ||
|
||||
name == "t2Bcc" ||
|
||||
name == "Bcc" ||
|
||||
name == "tCBZ" ||
|
||||
name == "tCBNZ") {
|
||||
BRANCH("target");
|
||||
}
|
||||
|
||||
if (name == "tBLr9" ||
|
||||
name == "BLr9_pred" ||
|
||||
name == "tBLXi_r9" ||
|
||||
name == "tBLXr_r9" ||
|
||||
name == "BLXr9" ||
|
||||
name == "t2BXJ" ||
|
||||
name == "BXJ") {
|
||||
BRANCH("func");
|
||||
|
||||
unsigned opIndex;
|
||||
opIndex = inst.getOperandNamed("func");
|
||||
if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
|
||||
operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
|
||||
}
|
||||
}
|
||||
|
||||
#undef BRANCH
|
||||
|
||||
/// populateInstInfo - Fills an array of InstInfos with information about each
|
||||
/// instruction in a target
|
||||
@@ -561,19 +750,29 @@ static void populateInstInfo(CompoundConstantEmitter &infoArray,
|
||||
CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
|
||||
infoArray.addEntry(infoStruct);
|
||||
|
||||
FlagsConstantEmitter *instFlags = new FlagsConstantEmitter;
|
||||
infoStruct->addEntry(instFlags);
|
||||
LiteralConstantEmitter *instType = new LiteralConstantEmitter;
|
||||
infoStruct->addEntry(instType);
|
||||
|
||||
LiteralConstantEmitter *numOperandsEmitter =
|
||||
new LiteralConstantEmitter(inst.OperandList.size());
|
||||
infoStruct->addEntry(numOperandsEmitter);
|
||||
|
||||
CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
|
||||
infoStruct->addEntry(operandTypeArray);
|
||||
|
||||
LiteralConstantEmitter *operandTypes[MAX_OPERANDS];
|
||||
|
||||
CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
|
||||
infoStruct->addEntry(operandFlagArray);
|
||||
|
||||
FlagsConstantEmitter *operandFlags[MAX_OPERANDS];
|
||||
|
||||
for (unsigned operandIndex = 0; operandIndex < MAX_OPERANDS; ++operandIndex) {
|
||||
for (unsigned operandIndex = 0;
|
||||
operandIndex < MAX_OPERANDS;
|
||||
++operandIndex) {
|
||||
operandTypes[operandIndex] = new LiteralConstantEmitter;
|
||||
operandTypeArray->addEntry(operandTypes[operandIndex]);
|
||||
|
||||
operandFlags[operandIndex] = new FlagsConstantEmitter;
|
||||
operandFlagArray->addEntry(operandFlags[operandIndex]);
|
||||
}
|
||||
@@ -581,29 +780,32 @@ static void populateInstInfo(CompoundConstantEmitter &infoArray,
|
||||
unsigned numSyntaxes = 0;
|
||||
|
||||
if (target.getName() == "X86") {
|
||||
X86PopulateOperands(operandFlags, inst);
|
||||
X86ExtractSemantics(*instFlags, operandFlags, inst);
|
||||
X86PopulateOperands(operandTypes, inst);
|
||||
X86ExtractSemantics(*instType, operandFlags, inst);
|
||||
numSyntaxes = 2;
|
||||
}
|
||||
else if (target.getName() == "ARM") {
|
||||
ARMPopulateOperands(operandTypes, inst);
|
||||
ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
|
||||
numSyntaxes = 1;
|
||||
}
|
||||
|
||||
CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
|
||||
|
||||
CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
|
||||
infoStruct->addEntry(operandOrderArray);
|
||||
|
||||
for (unsigned syntaxIndex = 0; syntaxIndex < MAX_SYNTAXES; ++syntaxIndex) {
|
||||
CompoundConstantEmitter *operandOrder = new CompoundConstantEmitter;
|
||||
CompoundConstantEmitter *operandOrder =
|
||||
new CompoundConstantEmitter(MAX_OPERANDS);
|
||||
|
||||
operandOrderArray->addEntry(operandOrder);
|
||||
|
||||
if (syntaxIndex < numSyntaxes) {
|
||||
populateOperandOrder(operandOrder, inst, syntaxIndex);
|
||||
}
|
||||
else {
|
||||
for (unsigned operandIndex = 0;
|
||||
operandIndex < MAX_OPERANDS;
|
||||
++operandIndex) {
|
||||
operandOrder->addEntry(new LiteralConstantEmitter("-1"));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
infoStruct = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -634,32 +836,71 @@ void EDEmitter::runHeader(raw_ostream &o) {
|
||||
|
||||
unsigned int i = 0;
|
||||
|
||||
EnumEmitter operandTypes("OperandTypes");
|
||||
operandTypes.addEntry("kOperandTypeNone");
|
||||
operandTypes.addEntry("kOperandTypeImmediate");
|
||||
operandTypes.addEntry("kOperandTypeRegister");
|
||||
operandTypes.addEntry("kOperandTypeX86Memory");
|
||||
operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
|
||||
operandTypes.addEntry("kOperandTypeX86PCRelative");
|
||||
operandTypes.addEntry("kOperandTypeARMBranchTarget");
|
||||
operandTypes.addEntry("kOperandTypeARMSoReg");
|
||||
operandTypes.addEntry("kOperandTypeARMSoImm");
|
||||
operandTypes.addEntry("kOperandTypeARMSoImm2Part");
|
||||
operandTypes.addEntry("kOperandTypeARMPredicate");
|
||||
operandTypes.addEntry("kOperandTypeARMAddrMode2");
|
||||
operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
|
||||
operandTypes.addEntry("kOperandTypeARMAddrMode3");
|
||||
operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
|
||||
operandTypes.addEntry("kOperandTypeARMAddrMode4");
|
||||
operandTypes.addEntry("kOperandTypeARMAddrMode5");
|
||||
operandTypes.addEntry("kOperandTypeARMAddrMode6");
|
||||
operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
|
||||
operandTypes.addEntry("kOperandTypeARMAddrModePC");
|
||||
operandTypes.addEntry("kOperandTypeARMRegisterList");
|
||||
operandTypes.addEntry("kOperandTypeARMTBAddrMode");
|
||||
operandTypes.addEntry("kOperandTypeThumbITMask");
|
||||
operandTypes.addEntry("kOperandTypeThumbAddrModeS1");
|
||||
operandTypes.addEntry("kOperandTypeThumbAddrModeS2");
|
||||
operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
|
||||
operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
|
||||
operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
|
||||
operandTypes.addEntry("kOperandTypeThumb2SoReg");
|
||||
operandTypes.addEntry("kOperandTypeThumb2SoImm");
|
||||
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
|
||||
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
|
||||
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
|
||||
operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
|
||||
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
|
||||
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
|
||||
|
||||
operandTypes.emit(o, i);
|
||||
|
||||
o << "\n";
|
||||
|
||||
EnumEmitter operandFlags("OperandFlags");
|
||||
operandFlags.addEntry("kOperandFlagImmediate");
|
||||
operandFlags.addEntry("kOperandFlagRegister");
|
||||
operandFlags.addEntry("kOperandFlagMemory");
|
||||
operandFlags.addEntry("kOperandFlagEffectiveAddress");
|
||||
operandFlags.addEntry("kOperandFlagPCRelative");
|
||||
operandFlags.addEntry("kOperandFlagSource");
|
||||
operandFlags.addEntry("kOperandFlagTarget");
|
||||
operandFlags.emitAsFlags(o, i);
|
||||
|
||||
o << "\n";
|
||||
|
||||
EnumEmitter instructionFlags("InstructionFlags");
|
||||
instructionFlags.addEntry("kInstructionFlagMove");
|
||||
instructionFlags.addEntry("kInstructionFlagBranch");
|
||||
instructionFlags.addEntry("kInstructionFlagPush");
|
||||
instructionFlags.addEntry("kInstructionFlagPop");
|
||||
instructionFlags.addEntry("kInstructionFlagCall");
|
||||
instructionFlags.addEntry("kInstructionFlagReturn");
|
||||
instructionFlags.emitAsFlags(o, i);
|
||||
EnumEmitter instructionTypes("InstructionTypes");
|
||||
instructionTypes.addEntry("kInstructionTypeNone");
|
||||
instructionTypes.addEntry("kInstructionTypeMove");
|
||||
instructionTypes.addEntry("kInstructionTypeBranch");
|
||||
instructionTypes.addEntry("kInstructionTypePush");
|
||||
instructionTypes.addEntry("kInstructionTypePop");
|
||||
instructionTypes.addEntry("kInstructionTypeCall");
|
||||
instructionTypes.addEntry("kInstructionTypeReturn");
|
||||
instructionTypes.emit(o, i);
|
||||
|
||||
o << "\n";
|
||||
|
||||
StructEmitter instInfo("InstInfo");
|
||||
instInfo.addMember("uint32_t", "instructionFlags");
|
||||
instInfo.addMember("uint8_t", "instructionType");
|
||||
instInfo.addMember("uint8_t", "numOperands");
|
||||
instInfo.addMember("uint8_t", "operandTypes[MAX_OPERANDS]");
|
||||
instInfo.addMember("uint8_t", "operandFlags[MAX_OPERANDS]");
|
||||
instInfo.addMember("const char", "operandOrders[MAX_SYNTAXES][MAX_OPERANDS]");
|
||||
instInfo.emit(o, i);
|
||||
|
||||
Reference in New Issue
Block a user