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Convert some missed patterns to support AT&T style
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16645 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -665,21 +665,21 @@ def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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"or{l} {$src2, $dst|$dst, $src2}">;
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let isTwoAddress = 0 in {
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def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
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"or{b} $dst, $src">;
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"or{b} {$src, $dst|$dst, $src}">;
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def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src),
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"or{w} $dst, $src">, OpSize;
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"or{w} {$src, $dst|$dst, $src}">, OpSize;
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def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src),
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"or{l} $dst, $src">;
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"or{l} {$src, $dst|$dst, $src}">;
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def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
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"or{b} $dst, $src">;
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"or{b} {$src, $dst|$dst, $src}">;
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def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
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"or{w} $dst, $src">, OpSize;
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"or{w} {$src, $dst|$dst, $src}">, OpSize;
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def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
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"or{l} $dst, $src">;
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"or{l} {$src, $dst|$dst, $src}">;
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def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i8imm:$src),
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"or{w} $dst, $src">, OpSize;
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"or{w} {$src, $dst|$dst, $src}">, OpSize;
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def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i8imm:$src),
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"or{l} $dst, $src">;
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"or{l} {$src, $dst|$dst, $src}">;
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}
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