From 8f9c5cca4feb71471dda44d9ba39a0ca644ddd6e Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Wed, 24 Aug 2011 13:32:43 +0000 Subject: [PATCH] Add Uses=[SP] to call instructions. This fixes a miscompilation with a variable sized alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138433 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/XCore/XCoreInstrInfo.td | 4 ++-- .../XCore/2011-08-01-DynamicAllocBug.ll | 20 +++++++++++++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index a1ec8aad87b..a9604692466 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -739,7 +739,7 @@ def LDAP_lu10_ba : _FLU10<(outs), let isCall=1, // All calls clobber the link register and the non-callee-saved registers: -Defs = [R0, R1, R2, R3, R11, LR] in { +Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { def BL_u10 : _FU10< (outs), (ins calltarget:$target, variable_ops), @@ -981,7 +981,7 @@ def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), let isCall=1, // All calls clobber the link register and the non-callee-saved registers: -Defs = [R0, R1, R2, R3, R11, LR] in { +Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), "bla $addr", [(XCoreBranchLink GRRegs:$addr)]>; diff --git a/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll b/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll new file mode 100644 index 00000000000..7d6d7bac3d6 --- /dev/null +++ b/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=xcore | FileCheck %s + +declare void @g() +declare i8* @llvm.stacksave() nounwind +declare void @llvm.stackrestore(i8*) nounwind + +define void @f(i32** %p, i32 %size) { +allocas: + %0 = call i8* @llvm.stacksave() + %a = alloca i32, i32 %size + store i32* %a, i32** %p + call void @g() + call void @llvm.stackrestore(i8* %0) + ret void +} +; CHECK: f: +; CHECK: ldaw [[REGISTER:r[0-9]+]], {{r[0-9]+}}[-r1] +; CHECK: set sp, [[REGISTER]] +; CHECK extsp 1 +; CHECK bl g