mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-06 09:44:39 +00:00
Remove trailing white space and tab characters. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162192 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
d60cb11afd
commit
8f9c7417b4
@ -20,21 +20,21 @@ multiclass fma3p_rm<bits<8> opc, string OpcodeStr> {
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let neverHasSideEffects = 1 in {
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def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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let mayLoad = 1 in
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def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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let mayLoad = 1 in
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def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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} // neverHasSideEffects = 1
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}
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@ -42,8 +42,8 @@ let neverHasSideEffects = 1 in {
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// Intrinsic for 213 pattern
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multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
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PatFrag MemFrag128, PatFrag MemFrag256,
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Intrinsic Int128, Intrinsic Int256, SDNode Op213,
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ValueType OpVT128, ValueType OpVT256> {
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Intrinsic Int128, Intrinsic Int256, SDNode Op213,
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ValueType OpVT128, ValueType OpVT256> {
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def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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@ -55,7 +55,7 @@ multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst, (OpVT128 (Op213 VR128:$src2,
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[(set VR128:$dst, (OpVT128 (Op213 VR128:$src2,
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VR128:$src1, VR128:$src3)))]>;
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def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
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@ -67,7 +67,7 @@ multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
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def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst, (OpVT128 (Op213 VR128:$src2, VR128:$src1,
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(MemFrag128 addr:$src3))))]>;
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@ -75,31 +75,31 @@ multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
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def rY_Int : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR256:$dst, (Int256 VR256:$src2, VR256:$src1,
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[(set VR256:$dst, (Int256 VR256:$src2, VR256:$src1,
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VR256:$src3))]>;
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def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR256:$dst, (OpVT256 (Op213 VR256:$src2, VR256:$src1,
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VR256:$src3)))]>;
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def mY_Int : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR256:$dst, (Int256 VR256:$src2, VR256:$src1,
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[(set VR256:$dst, (Int256 VR256:$src2, VR256:$src1,
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(MemFrag256 addr:$src3)))]>;
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def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, f256mem:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR256:$dst,
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(OpVT256 (Op213 VR256:$src2, VR256:$src1,
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(OpVT256 (Op213 VR256:$src2, VR256:$src1,
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(MemFrag256 addr:$src3))))]>;
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}
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} // Constraints = "$src1 = $dst"
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@ -112,9 +112,9 @@ multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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defm r213 : fma3p_rm_int <opc213, !strconcat(OpcodeStr,
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!strconcat("213", PackTy)), MemFrag128, MemFrag256,
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Int128, Int256, Op, OpTy128, OpTy256>;
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defm r132 : fma3p_rm <opc132,
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defm r132 : fma3p_rm <opc132,
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!strconcat(OpcodeStr, !strconcat("132", PackTy))>;
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defm r231 : fma3p_rm <opc231,
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defm r231 : fma3p_rm <opc231,
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!strconcat(OpcodeStr, !strconcat("231", PackTy))>;
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}
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@ -125,16 +125,16 @@ let ExeDomain = SSEPackedSingle in {
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int_x86_fma_vfmadd_ps_256, X86Fmadd,
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v4f32, v8f32>;
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defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", memopv4f32,
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memopv8f32, int_x86_fma_vfmsub_ps,
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memopv8f32, int_x86_fma_vfmsub_ps,
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int_x86_fma_vfmsub_ps_256, X86Fmsub,
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v4f32, v8f32>;
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defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
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memopv4f32, memopv8f32,
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memopv4f32, memopv8f32,
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int_x86_fma_vfmaddsub_ps,
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int_x86_fma_vfmaddsub_ps_256, X86Fmaddsub,
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int_x86_fma_vfmaddsub_ps_256, X86Fmaddsub,
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v4f32, v8f32>;
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defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
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memopv4f32, memopv8f32,
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memopv4f32, memopv8f32,
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int_x86_fma_vfmsubadd_ps,
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int_x86_fma_vfmaddsub_ps_256, X86Fmsubadd,
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v4f32, v8f32>;
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@ -155,7 +155,7 @@ let ExeDomain = SSEPackedDouble in {
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int_x86_fma_vfmaddsub_pd_256, X86Fmaddsub,
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v2f64, v4f64>, VEX_W;
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defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
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memopv2f64, memopv4f64,
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memopv2f64, memopv4f64,
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int_x86_fma_vfmsubadd_pd,
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int_x86_fma_vfmsubadd_pd_256, X86Fmsubadd,
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v2f64, v4f64>, VEX_W;
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@ -190,47 +190,47 @@ multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
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let neverHasSideEffects = 1 in {
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def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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let mayLoad = 1 in
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def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, x86memop:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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} // neverHasSideEffects = 1
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}
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multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
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ComplexPattern mem_cpat, Intrinsic IntId,
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ComplexPattern mem_cpat, Intrinsic IntId,
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RegisterClass RC, SDNode OpNode, ValueType OpVT> {
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def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst, (IntId VR128:$src2, VR128:$src1,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst, (IntId VR128:$src2, VR128:$src1,
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VR128:$src3))]>;
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def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, memop:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(IntId VR128:$src2, VR128:$src1, mem_cpat:$src3))]>;
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def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
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(OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
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let mayLoad = 1 in
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def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, memop:$src3),
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!strconcat(OpcodeStr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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}
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} // Constraints = "$src1 = $dst"
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multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
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string OpStr, Intrinsic IntF32, Intrinsic IntF64,
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string OpStr, Intrinsic IntF32, Intrinsic IntF64,
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SDNode OpNode> {
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defm SSr132 : fma3s_rm<opc132, !strconcat(OpStr, "132ss"), f32mem, FR32>;
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defm SSr231 : fma3s_rm<opc231, !strconcat(OpStr, "231ss"), f32mem, FR32>;
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