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Add frameindex support
Add support for copying (e.g. returning) doubles Add support for F<->I instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24818 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
abfc2a7363
commit
8fa54dc702
@ -14,6 +14,7 @@
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#include "SparcV8.h"
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#include "SparcV8TargetMachine.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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@ -36,6 +37,9 @@ namespace V8ISD {
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BRFCC, // Branch to dest on fcc condition
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Hi, Lo, // Hi/Lo operations, typically on a global address.
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FTOI, // FP to Int within a FP register.
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ITOF, // Int to FP within a FP register.
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};
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}
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@ -85,6 +89,14 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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// Sparc has no REM operation.
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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// Custom expand fp<->sint
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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// Expand fp<->uint
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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// Sparc has no select or setcc: expand to SELECT_CC.
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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@ -259,6 +271,31 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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}
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case ISD::FP_TO_SINT: {
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// Convert the fp value to integer in an FP register.
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Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(),
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Op.getOperand(0));
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int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
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int FrameIdx =
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DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
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SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
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Op, FI, DAG.getSrcValue(0));
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return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
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}
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case ISD::SINT_TO_FP: {
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int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
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int FrameIdx =
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DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
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SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
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Op.getOperand(0), FI, DAG.getSrcValue(0));
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Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0));
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// Convert the int value to FP in an FP register.
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return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
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}
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}
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}
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@ -311,8 +348,48 @@ void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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ScheduleAndEmitDAG(DAG);
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}
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bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
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SDOperand &Offset) {
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if (Addr.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Addr)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (Predicate_simm13(CN)) {
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if (Addr.getOperand(0).getOpcode() == ISD::FrameIndex) {
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// Constant offset from frame ref.
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int FI = cast<FrameIndexSDNode>(Addr)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, MVT::i32);
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} else {
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Base = Select(Addr.getOperand(0));
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}
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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}
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if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(1));
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(0));
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Select(Addr);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
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SDOperand &R2) {
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if (Addr.getOpcode() == ISD::FrameIndex) return false;
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if (Addr.getOpcode() == ISD::ADD) {
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).Val))
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@ -330,32 +407,6 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
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return true;
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}
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bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
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SDOperand &Offset) {
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if (Predicate_simm13(CN)) {
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Base = Select(Addr.getOperand(0));
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(1));
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(0));
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Select(Addr);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
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@ -368,6 +419,17 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::BasicBlock: return CodeGenMap[Op] = Op;
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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if (N->hasOneUse())
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return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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CurDAG->getTargetConstant(0, MVT::i32));
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return CodeGenMap[Op] =
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CurDAG->getTargetNode(V8::ADDri, MVT::i32,
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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CurDAG->getTargetConstant(0, MVT::i32));
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}
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case V8ISD::CMPICC: {
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// FIXME: Handle compare with immediate.
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SDOperand LHS = Select(N->getOperand(0));
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@ -87,6 +87,9 @@ def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
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def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
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def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
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def V8ftoi : SDNode<"V8ISD::FTOI", SDTFPUnaryOp>;
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def V8itof : SDNode<"V8ISD::ITOF", SDTFPUnaryOp>;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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@ -104,7 +107,8 @@ def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
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//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
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def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
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(ops IntRegs:$dst)>;
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def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
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def FpMOVD : PseudoInstV8<"!FpMOVD", // pseudo 64-bit double move
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(ops DFPRegs:$dst, DFPRegs:$src)>;
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// Section A.3 - Synthetic Instructions, p. 85
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// special cases of JMPL:
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@ -544,18 +548,22 @@ def WRYri : F3_2<2, 0b110000,
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// Convert Integer to Floating-point Instructions, p. 141
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def FITOS : F3_3<2, 0b110100, 0b011000100,
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(ops FPRegs:$dst, FPRegs:$src),
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"fitos $src, $dst", []>;
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"fitos $src, $dst",
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[(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
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def FITOD : F3_3<2, 0b110100, 0b011001000,
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(ops DFPRegs:$dst, DFPRegs:$src),
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"fitod $src, $dst", []>;
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"fitod $src, $dst",
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[(set DFPRegs:$dst, (V8itof DFPRegs:$src))]>;
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// Convert Floating-point to Integer Instructions, p. 142
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def FSTOI : F3_3<2, 0b110100, 0b011010001,
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(ops FPRegs:$dst, FPRegs:$src),
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"fstoi $src, $dst", []>;
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"fstoi $src, $dst",
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[(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
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def FDTOI : F3_3<2, 0b110100, 0b011010010,
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(ops DFPRegs:$dst, DFPRegs:$src),
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"fdtoi $src, $dst", []>;
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"fdtoi $src, $dst",
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[(set DFPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
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// Convert between Floating-point Formats Instructions, p. 143
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def FSTOD : F3_3<2, 0b110100, 0b011001001,
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@ -14,6 +14,7 @@
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#include "SparcV8.h"
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#include "SparcV8TargetMachine.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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@ -36,6 +37,9 @@ namespace V8ISD {
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BRFCC, // Branch to dest on fcc condition
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Hi, Lo, // Hi/Lo operations, typically on a global address.
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FTOI, // FP to Int within a FP register.
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ITOF, // Int to FP within a FP register.
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};
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}
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@ -85,6 +89,14 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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// Sparc has no REM operation.
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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// Custom expand fp<->sint
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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// Expand fp<->uint
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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// Sparc has no select or setcc: expand to SELECT_CC.
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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@ -259,6 +271,31 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
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return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
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}
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case ISD::FP_TO_SINT: {
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// Convert the fp value to integer in an FP register.
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Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(),
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Op.getOperand(0));
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int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
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int FrameIdx =
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DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
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SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
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Op, FI, DAG.getSrcValue(0));
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return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
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}
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case ISD::SINT_TO_FP: {
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int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
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int FrameIdx =
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DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
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SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
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Op.getOperand(0), FI, DAG.getSrcValue(0));
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Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0));
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// Convert the int value to FP in an FP register.
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return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
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}
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}
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}
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@ -311,8 +348,48 @@ void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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ScheduleAndEmitDAG(DAG);
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}
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bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
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SDOperand &Offset) {
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if (Addr.getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(Addr)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (Predicate_simm13(CN)) {
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if (Addr.getOperand(0).getOpcode() == ISD::FrameIndex) {
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// Constant offset from frame ref.
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int FI = cast<FrameIndexSDNode>(Addr)->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, MVT::i32);
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} else {
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Base = Select(Addr.getOperand(0));
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}
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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}
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if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(1));
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(0));
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Select(Addr);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
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SDOperand &R2) {
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if (Addr.getOpcode() == ISD::FrameIndex) return false;
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if (Addr.getOpcode() == ISD::ADD) {
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).Val))
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@ -330,32 +407,6 @@ bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
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return true;
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}
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bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
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SDOperand &Offset) {
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if (Predicate_simm13(CN)) {
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Base = Select(Addr.getOperand(0));
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(1));
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
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Base = Select(Addr.getOperand(0));
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Select(Addr);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
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@ -368,6 +419,17 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::BasicBlock: return CodeGenMap[Op] = Op;
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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if (N->hasOneUse())
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return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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CurDAG->getTargetConstant(0, MVT::i32));
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return CodeGenMap[Op] =
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CurDAG->getTargetNode(V8::ADDri, MVT::i32,
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
|
||||
CurDAG->getTargetConstant(0, MVT::i32));
|
||||
}
|
||||
case V8ISD::CMPICC: {
|
||||
// FIXME: Handle compare with immediate.
|
||||
SDOperand LHS = Select(N->getOperand(0));
|
||||
|
||||
@ -87,6 +87,9 @@ def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
|
||||
def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
|
||||
def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
|
||||
|
||||
def V8ftoi : SDNode<"V8ISD::FTOI", SDTFPUnaryOp>;
|
||||
def V8itof : SDNode<"V8ISD::ITOF", SDTFPUnaryOp>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -104,7 +107,8 @@ def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
|
||||
//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
|
||||
def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
|
||||
(ops IntRegs:$dst)>;
|
||||
def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
|
||||
def FpMOVD : PseudoInstV8<"!FpMOVD", // pseudo 64-bit double move
|
||||
(ops DFPRegs:$dst, DFPRegs:$src)>;
|
||||
|
||||
// Section A.3 - Synthetic Instructions, p. 85
|
||||
// special cases of JMPL:
|
||||
@ -544,18 +548,22 @@ def WRYri : F3_2<2, 0b110000,
|
||||
// Convert Integer to Floating-point Instructions, p. 141
|
||||
def FITOS : F3_3<2, 0b110100, 0b011000100,
|
||||
(ops FPRegs:$dst, FPRegs:$src),
|
||||
"fitos $src, $dst", []>;
|
||||
"fitos $src, $dst",
|
||||
[(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
|
||||
def FITOD : F3_3<2, 0b110100, 0b011001000,
|
||||
(ops DFPRegs:$dst, DFPRegs:$src),
|
||||
"fitod $src, $dst", []>;
|
||||
"fitod $src, $dst",
|
||||
[(set DFPRegs:$dst, (V8itof DFPRegs:$src))]>;
|
||||
|
||||
// Convert Floating-point to Integer Instructions, p. 142
|
||||
def FSTOI : F3_3<2, 0b110100, 0b011010001,
|
||||
(ops FPRegs:$dst, FPRegs:$src),
|
||||
"fstoi $src, $dst", []>;
|
||||
"fstoi $src, $dst",
|
||||
[(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
|
||||
def FDTOI : F3_3<2, 0b110100, 0b011010010,
|
||||
(ops DFPRegs:$dst, DFPRegs:$src),
|
||||
"fdtoi $src, $dst", []>;
|
||||
"fdtoi $src, $dst",
|
||||
[(set DFPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
|
||||
|
||||
// Convert between Floating-point Formats Instructions, p. 143
|
||||
def FSTOD : F3_3<2, 0b110100, 0b011001001,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user