diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 7acdfc7bdc8..d53e66da5a7 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -80,12 +80,12 @@ public: virtual SDNode *Select(SDNode *N) = 0; /// SelectInlineAsmMemoryOperand - Select the specified address as a target - /// addressing mode, according to the specified constraint. If this does + /// addressing mode, according to the specified constraint code. If this does /// not match or is not implemented, return true. The resultant operands /// (which will appear in the machine instruction) should be added to the /// OutOps vector. virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + char ConstraintCode, std::vector &OutOps) { return true; } diff --git a/include/llvm/IR/InlineAsm.h b/include/llvm/IR/InlineAsm.h index 4c01ef00d3e..84ae9df9715 100644 --- a/include/llvm/IR/InlineAsm.h +++ b/include/llvm/IR/InlineAsm.h @@ -189,19 +189,6 @@ public: // These are helper methods for dealing with flags in the INLINEASM SDNode // in the backend. - // - // The encoding of the flag word is currently: - // Bits 2-0 - A Kind_* value indicating the kind of the operand. - // Bits 15-3 - The number of SDNode operands associated with this inline - // assembly operand. - // If bits 2-0 are Kind_Mem: - // Bit 31 - 0 - // Bit 30-16 - A Constraint_* value indicating the original constraint - // code. - // Else if bit 31 is set: - // Bit 30-16 - The operand number that this operand must match. - // Else if bit 31 is clear: - // Bit 30-16 - The register class ID to use for the operand. enum : uint32_t { // Fixed operands on an INLINEASM SDNode. @@ -233,17 +220,6 @@ public: Kind_Imm = 5, // Immediate. Kind_Mem = 6, // Memory operand, "m". - // Memory constraint codes. - // These could be tablegenerated but there's little need to do that since - // there's plenty of space in the encoding to support the union of all - // constraint codes for all targets. - Constraint_Unknown = 0, - Constraint_m, - Constraint_o, // Unused at the moment since Constraint_m is always used. - Constraint_v, // Unused at the moment since Constraint_m is always used. - Constraints_Max = Constraint_v, - Constraints_ShiftAmount = 16, - Flag_MatchingOperand = 0x80000000 }; @@ -276,15 +252,6 @@ public: return InputFlag | (RC << 16); } - /// Augment an existing flag word returned by getFlagWord with the constraint - /// code for a memory constraint. - static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) { - assert(Constraint <= 0x7fff && "Too large a memory constraint ID"); - assert(Constraint <= Constraints_Max && "Unknown constraint ID"); - assert((InputFlag & ~0xffff) == 0 && "High bits already contain data"); - return InputFlag | (Constraint << Constraints_ShiftAmount); - } - static unsigned getKind(unsigned Flags) { return Flags & 7; } @@ -299,11 +266,6 @@ public: return getKind(Flag) == Kind_Clobber; } - static unsigned getMemoryConstraintID(unsigned Flag) { - assert(isMemKind(Flag)); - return (Flag >> Constraints_ShiftAmount) & 0x7fff; - } - /// getNumOperandRegisters - Extract the number of registers field from the /// inline asm operand flag. static unsigned getNumOperandRegisters(unsigned Flag) { diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 4e08cc961be..5a4253dcd50 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -2625,13 +2625,6 @@ public: getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, const std::string &Constraint, MVT VT) const; - virtual unsigned - getInlineAsmMemConstraint(const std::string &ConstraintCode) const { - // FIXME: This currently maps all constraints to the the same code. - // This will be corrected once all targets are updated. - return InlineAsm::Constraint_m; - } - /// Try to replace an X constraint, which matches anything, with another that /// has more specific requirements based on the type of the corresponding /// operand. This returns null if there is no replacement to make. diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index d4d449a2e05..1face070ce7 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -6595,14 +6595,8 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { // Memory output, or 'other' output (e.g. 'X' constraint). assert(OpInfo.isIndirect && "Memory output must be indirect operand"); - unsigned ConstraintID = - TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); - assert(ConstraintID != InlineAsm::Constraint_Unknown && - "Failed to convert memory constraint code to constraint id."); - // Add information to the INLINEASM node to know about this output. unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); - OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID); AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, MVT::i32)); AsmNodeOperands.push_back(OpInfo.CallOperand); break; @@ -6746,14 +6740,8 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { assert(InOperandVal.getValueType() == TLI.getPointerTy() && "Memory operands expect pointer values"); - unsigned ConstraintID = - TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode); - assert(ConstraintID != InlineAsm::Constraint_Unknown && - "Failed to convert memory constraint code to constraint id."); - // Add information to the INLINEASM node to know about this input. unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); - ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID); AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, MVT::i32)); AsmNodeOperands.push_back(InOperandVal); break; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 6f8677d657c..97abe32c972 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -1781,9 +1781,7 @@ SelectInlineAsmMemoryOperands(std::vector &Ops) { "Memory operand with multiple values?"); // Otherwise, this is a memory operand. Ask the target to select it. std::vector SelOps; - if (SelectInlineAsmMemoryOperand(InOps[i+1], - InlineAsm::getMemoryConstraintID(Flags), - SelOps)) + if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) report_fatal_error("Could not match memory address. Inline asm" " failure!"); diff --git a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index f401b70e0f8..01524ad22c2 100644 --- a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -65,7 +65,7 @@ public: /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + char ConstraintCode, std::vector &OutOps) override; SDNode *SelectMLAV64LaneV128(SDNode *N); @@ -211,9 +211,8 @@ static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc, } bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand( - const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { - assert(ConstraintID == InlineAsm::Constraint_m && - "unexpected asm memory constraint"); + const SDValue &Op, char ConstraintCode, std::vector &OutOps) { + assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); // Require the address to be in a register. That is safe for all AArch64 // variants and it is hard to do anything much smarter without knowing // how the operand is used. diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 44cd1ef8052..a32055df19f 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -257,7 +257,7 @@ private: /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) override; // Form pairs of consecutive R, S, D, or Q registers. @@ -3472,10 +3472,9 @@ SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){ bool ARMDAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, +SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) { - assert(ConstraintID == InlineAsm::Constraint_m && - "unexpected asm memory constraint"); + assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); // Require the address to be in a register. That is safe for all ARM // variants and it is hard to do anything much smarter without knowing // how the operand is used. diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 795faf97af4..a3e753a89cb 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -71,7 +71,7 @@ public: /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + char ConstraintCode, std::vector &OutOps) override; SDNode *SelectLoad(SDNode *N); SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl); @@ -1103,16 +1103,16 @@ SDNode *HexagonDAGToDAGISel::Select(SDNode *N) { bool HexagonDAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, +SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) { SDValue Inp = Op, Res; - switch (ConstraintID) { - case InlineAsm::Constraint_o: // Offsetable. - case InlineAsm::Constraint_v: // Not offsetable. + switch (ConstraintCode) { + case 'o': // Offsetable. + case 'v': // Not offsetable. default: return true; - case InlineAsm::Constraint_m: // Memory. + case 'm': // Memory. if (SelectAddrFI(Inp, Res)) OutOps.push_back(Res); else diff --git a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 591ceb55d57..2f70cde75d4 100644 --- a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -104,7 +104,7 @@ namespace { bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM); bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM); - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) override; // Include the pieces autogenerated from the target description. @@ -280,12 +280,12 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue N, } bool MSP430DAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, +SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) { SDValue Op0, Op1; - switch (ConstraintID) { + switch (ConstraintCode) { default: return true; - case InlineAsm::Constraint_m: // memory + case 'm': // memory if (!SelectAddr(Op, Op0, Op1)) return true; break; diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index 50776f9015b..21fc8ce2d58 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -230,10 +230,9 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) { } bool MipsDAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, +SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) { - assert(ConstraintID == InlineAsm::Constraint_m && - "unexpected asm memory constraint"); + assert(ConstraintCode == 'm' && "unexpected asm memory constraint"); OutOps.push_back(Op); return false; } diff --git a/lib/Target/Mips/MipsISelDAGToDAG.h b/lib/Target/Mips/MipsISelDAGToDAG.h index aec731e0dff..6b72877e9ee 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.h +++ b/lib/Target/Mips/MipsISelDAGToDAG.h @@ -125,7 +125,7 @@ private: virtual void processFunctionAfterISel(MachineFunction &MF) = 0; bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + char ConstraintCode, std::vector &OutOps) override; }; } diff --git a/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp index 62ae664804d..e01c7801507 100644 --- a/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp +++ b/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp @@ -5044,12 +5044,12 @@ bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N, /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand( - const SDValue &Op, unsigned ConstraintID, std::vector &OutOps) { + const SDValue &Op, char ConstraintCode, std::vector &OutOps) { SDValue Op0, Op1; - switch (ConstraintID) { + switch (ConstraintCode) { default: return true; - case InlineAsm::Constraint_m: // memory + case 'm': // memory if (SelectDirectAddr(Op, Op0)) { OutOps.push_back(Op0); OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32)); diff --git a/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/lib/Target/NVPTX/NVPTXISelDAGToDAG.h index 6d845c9d5d1..ca432b53be8 100644 --- a/lib/Target/NVPTX/NVPTXISelDAGToDAG.h +++ b/lib/Target/NVPTX/NVPTXISelDAGToDAG.h @@ -48,7 +48,7 @@ public: const NVPTXSubtarget *Subtarget; bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + char ConstraintCode, std::vector &OutOps) override; private: // Include the pieces autogenerated from the target description. diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index f8b211ec351..4bd303f211d 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -186,7 +186,7 @@ namespace { /// register can be improved, but it is wrong to substitute Reg+Reg for /// Reg in an asm, because the load or store opcode would have to change. bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + char ConstraintCode, std::vector &OutOps) override { // We need to make sure that this one operand does not end up in r0 // (because we might end up lowering this as 0(%op)). diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index c004ad9e626..9f03b04f8d4 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -50,7 +50,7 @@ public: /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + char ConstraintCode, std::vector &OutOps) override; const char *getPassName() const override { @@ -195,12 +195,12 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) { /// inline asm expressions. bool SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + char ConstraintCode, std::vector &OutOps) { SDValue Op0, Op1; - switch (ConstraintID) { + switch (ConstraintCode) { default: return true; - case InlineAsm::Constraint_m: // memory + case 'm': // memory if (!SelectADDRrr(Op, Op0, Op1)) SelectADDRri(Op, Op0, Op1); break; diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index cd0cac69c9b..b8b0db9e8c7 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -328,7 +328,7 @@ public: // Override SelectionDAGISel. SDNode *Select(SDNode *Node) override; - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) override; // Include the pieces autogenerated from the target description. @@ -1129,10 +1129,9 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) { bool SystemZDAGToDAGISel:: SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + char ConstraintCode, std::vector &OutOps) { - assert(ConstraintID == InlineAsm::Constraint_m && - "Unexpected constraint code"); + assert(ConstraintCode == 'm' && "Unexpected constraint code"); // Accept addresses with short displacements, which are compatible // with Q, R, S and T. But keep the index operand for future expansion. SDValue Base, Disp, Index; diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index fb12ce51db2..42715562a7c 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -228,7 +228,7 @@ namespace { /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. bool SelectInlineAsmMemoryOperand(const SDValue &Op, - unsigned ConstraintID, + char ConstraintCode, std::vector &OutOps) override; void EmitSpecialCodeForMain(); @@ -2814,14 +2814,14 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) { } bool X86DAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, +SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) { SDValue Op0, Op1, Op2, Op3, Op4; - switch (ConstraintID) { - case InlineAsm::Constraint_o: // offsetable ?? - case InlineAsm::Constraint_v: // not offsetable ?? + switch (ConstraintCode) { + case 'o': // offsetable ?? + case 'v': // not offsetable ?? default: return true; - case InlineAsm::Constraint_m: // memory + case 'm': // memory if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4)) return true; break; diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp index 5c7ea5e3640..f79b78bdd2a 100644 --- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -65,7 +65,7 @@ namespace { // Complex Pattern Selectors. bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset); - bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) override; const char *getPassName() const override { @@ -108,12 +108,12 @@ bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, } bool XCoreDAGToDAGISel:: -SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, +SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, std::vector &OutOps) { SDValue Reg; - switch (ConstraintID) { + switch (ConstraintCode) { default: return true; - case InlineAsm::Constraint_m: // Memory. + case 'm': // Memory. switch (Op.getOpcode()) { default: return true; case XCoreISD::CPRelativeWrapper: