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Fix buglet when the TST instruction directly uses the AND result.

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I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114430 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Gabor Greif 2010-09-21 13:30:57 +00:00
parent e9c935662d
commit 8ff9bb189c
1 changed files with 6 additions and 5 deletions
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11
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -1399,12 +1399,13 @@ AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, int &CmpV
}
static bool isSuitableForMask(const MachineInstr &MI, unsigned SrcReg,
int CmpMask) {
int CmpMask, bool CommonUse) {
switch (MI.getOpcode()) {
case ARM::ANDri:
case ARM::t2ANDri:
if (SrcReg == MI.getOperand(1).getReg() &&
CmpMask == MI.getOperand(2).getImm())
if (CmpMask != MI.getOperand(2).getImm())
return false;
if (SrcReg == MI.getOperand(CommonUse ? 1 : 0).getReg())
return true;
break;
}
@ -1431,13 +1432,13 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
// Masked compares sometimes use the same register as the corresponding 'and'.
if (CmpMask != ~0) {
if (!isSuitableForMask(*MI, SrcReg, CmpMask)) {
if (!isSuitableForMask(*MI, SrcReg, CmpMask, false)) {
MI = 0;
for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
UE = MRI.use_end(); UI != UE; ++UI) {
if (UI->getParent() != CmpInstr->getParent()) continue;
MachineInstr &PotentialAND = *UI;
if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask))
if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
continue;
SrcReg = PotentialAND.getOperand(0).getReg();
MI = &PotentialAND;