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Implement more complete and correct codegen for bitfield inserts, as tested
by the recently committed rlwimi.ll test file. Also commit initial code for bitfield extract, although it is turned off until fully debugged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17207 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
2a40841387
commit
905a29152f
@ -32,8 +32,6 @@
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using namespace llvm;
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namespace {
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Statistic<> Bitfields("ppc-codegen", "Number of bitfield inserts");
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/// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
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/// PPC Representation.
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///
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@ -99,19 +97,18 @@ namespace {
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FoldedGEP(unsigned b, unsigned i, ConstantSInt *o) :
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base(b), index(i), offset(o) {}
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};
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/// RlwimiRec - This struct is for recording the necessary information to
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/// emit a PowerPC rlwimi instruction for a bitfield insert rather than
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/// a sequence of shifts and ands, followed by an or.
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struct RlwimiRec {
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unsigned Shift;
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unsigned MB, ME;
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Value *Op0, *Op1;
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RlwimiRec() : Shift(0), MB(0), ME(0), Op0(0), Op1(0) {}
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RlwimiRec(unsigned s, unsigned b, unsigned e, Value *y, Value *z) :
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Shift(s), MB(b), ME(e), Op0(y), Op1(z) {}
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/// RlwimiRec - This struct is for recording the arguments to a PowerPC
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/// rlwimi instruction to be output for a particular Instruction::Or when
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/// we recognize the pattern for rlwimi, starting with a shift or and.
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struct RlwimiRec {
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Value *Target, *Insert;
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unsigned Shift, MB, ME;
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RlwimiRec() : Target(0), Insert(0), Shift(0), MB(0), ME(0) {}
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RlwimiRec(Value *tgt, Value *ins, unsigned s, unsigned b, unsigned e) :
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Target(tgt), Insert(ins), Shift(s), MB(b), ME(e) {}
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};
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// External functions used in the Module
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Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
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*__umoddi3Fn, *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
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@ -132,7 +129,11 @@ namespace {
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// RlwimiMap - Mapping between BinaryOperand (Or) instructions and info
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// needed to properly emit a rlwimi instruction in its place.
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std::map<BinaryOperator *, RlwimiRec> RlwimiMap;
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std::map<Instruction *, RlwimiRec> InsertMap;
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// A rlwimi instruction is the combination of at least three instructions.
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// Keep a vector of instructions to skip around so that we do not try to
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// emit instructions that were folded into a rlwimi.
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std::vector<Instruction *> SkipList;
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// A Reg to hold the base address used for global loads and stores, and a
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@ -215,8 +216,8 @@ namespace {
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GEPMap.clear();
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RegMap.clear();
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MBBMap.clear();
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InsertMap.clear();
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AllocaMap.clear();
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RlwimiMap.clear();
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SkipList.clear();
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F = 0;
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// We always build a machine code representation for the function
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@ -339,10 +340,18 @@ namespace {
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/// emitBitfieldInsert - return true if we were able to fold the sequence of
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/// instructions starting with AndI into a bitfield insert.
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bool PPC32ISel::emitBitfieldInsert(BinaryOperator *AndI,
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unsigned ShlAmount,
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Value *InsertOp);
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/// instructions into a bitfield insert (rlwimi).
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bool emitBitfieldInsert(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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User *OpUser, unsigned DestReg);
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/// emitBitfieldExtract - return true if we were able to fold the sequence
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/// of instructions into a bitfield extract (rlwinm).
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bool emitBitfieldExtract(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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BinaryOperator *AndI, Value *Op,
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unsigned Amount, bool isLeftShift,
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unsigned DestReg);
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/// emitBinaryConstOperation - Used by several functions to emit simple
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/// arithmetic and logical operations with constants on a register rather
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@ -359,8 +368,7 @@ namespace {
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///
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void emitSimpleBinaryOperation(MachineBasicBlock *BB,
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MachineBasicBlock::iterator IP,
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BinaryOperator *BO,
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Value *Op0, Value *Op1,
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BinaryOperator *BO, Value *Op0, Value *Op1,
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unsigned OperatorClass, unsigned TargetReg);
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/// emitBinaryFPOperation - This method handles emission of floating point
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@ -2021,23 +2029,23 @@ void PPC32ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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/// Xor.
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///
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void PPC32ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
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unsigned DestReg = getReg(B);
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MachineBasicBlock::iterator MI = BB->end();
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Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
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unsigned Class = getClassB(B.getType());
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if (std::find(SkipList.begin(), SkipList.end(), &B) != SkipList.end())
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return;
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RlwimiRec r = RlwimiMap[&B];
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if (0 != r.Op0) {
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unsigned Op0Reg = getReg(r.Op0, BB, MI);
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unsigned Op1Reg = getReg(r.Op1, BB, MI);
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BuildMI(*BB, MI, PPC::RLWIMI, 5, DestReg).addReg(Op1Reg)
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.addReg(Op0Reg).addImm(r.Shift).addImm(r.MB).addImm(r.ME);
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} else {
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emitSimpleBinaryOperation(BB, MI, &B, Op0, Op1, OperatorClass, DestReg);
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unsigned DestReg = getReg(B);
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MachineBasicBlock::iterator MI = BB->end();
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RlwimiRec RR = InsertMap[&B];
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if (RR.Target != 0) {
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unsigned TargetReg = getReg(RR.Target, BB, MI);
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unsigned InsertReg = getReg(RR.Insert, BB, MI);
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BuildMI(*BB, MI, PPC::RLWIMI, 5, DestReg).addReg(TargetReg)
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.addReg(InsertReg).addImm(RR.Shift).addImm(RR.MB).addImm(RR.ME);
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return;
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}
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unsigned Class = getClassB(B.getType());
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Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
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emitSimpleBinaryOperation(BB, MI, &B, Op0, Op1, OperatorClass, DestReg);
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}
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/// emitBinaryFPOperation - This method handles emission of floating point
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@ -2134,52 +2142,189 @@ static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
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return false;
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}
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/// emitBitfieldInsert - return true if we were able to fold the sequence of
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/// instructions starting with AndI into a bitfield insert.
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bool PPC32ISel::emitBitfieldInsert(BinaryOperator *AndI, unsigned ShlAmount,
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Value *InsertOp) {
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if (AndI->hasOneUse()) {
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ConstantInt *CI_1 = dyn_cast<ConstantInt>(AndI->getOperand(1));
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BinaryOperator *OrI = dyn_cast<BinaryOperator>(*(AndI->use_begin()));
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if (CI_1 && OrI && OrI->getOpcode() == Instruction::Or) {
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Value *Op0 = OrI->getOperand(0);
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Value *Op1 = OrI->getOperand(1);
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BinaryOperator *AndI_2 = 0;
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// Whichever operand our initial And instruction is to the Or instruction,
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// Look at the other operand to determine if it is also an And instruction
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if (AndI == Op0) {
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AndI_2 = dyn_cast<BinaryOperator>(Op1);
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} else if (AndI == Op1) {
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AndI_2 = dyn_cast<BinaryOperator>(Op0);
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std::swap(Op0, Op1);
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} else {
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assert(0 && "And instruction not used in Or!");
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}
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// Verify that the second operand to the Or is an And with one use
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if (AndI_2 && AndI_2->hasOneUse()
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&& AndI_2->getOpcode() == Instruction::And) {
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// Check to see if this And instruction also has a constant int operand.
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// If it does, then we can replace this sequence of instructions with an
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// insert if the sum of the two ConstantInts has all bits set, and
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// one is a run of ones (which implies the other is as well).
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ConstantInt *CI_2 = dyn_cast<ConstantInt>(AndI_2->getOperand(1));
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if (CI_2) {
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unsigned Imm1 = CI_1->getRawValue();
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unsigned Imm2 = CI_2->getRawValue();
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if (Imm1 + Imm2 == 0xFFFFFFFF) {
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unsigned MB, ME;
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if (isRunOfOnes(Imm1, MB, ME)) {
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++Bitfields;
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SkipList.push_back(AndI);
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SkipList.push_back(AndI_2);
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RlwimiMap[OrI] = RlwimiRec(ShlAmount, MB, ME,
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InsertOp, AndI_2->getOperand(0));
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return true;
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/// isInsertAndHalf - Helper function for emitBitfieldInsert. Returns true if
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/// OpUser has one use, is used by an or instruction, and is itself an and whose
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/// second operand is a constant int. Optionally, set OrI to the Or instruction
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/// that is the sole user of OpUser, and Op1User to the other operand of the Or
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/// instruction.
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static bool isInsertAndHalf(User *OpUser, Instruction **Op1User,
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Instruction **OrI, unsigned &Mask) {
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// If this instruction doesn't have one use, then return false.
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if (!OpUser->hasOneUse())
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return false;
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Mask = 0xFFFFFFFF;
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if (BinaryOperator *BO = dyn_cast<BinaryOperator>(OpUser))
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if (BO->getOpcode() == Instruction::And) {
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Value *AndUse = *(OpUser->use_begin());
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if (BinaryOperator *Or = dyn_cast<BinaryOperator>(AndUse)) {
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if (Or->getOpcode() == Instruction::Or) {
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if (ConstantInt *CI = dyn_cast<ConstantInt>(OpUser->getOperand(1))) {
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if (OrI) *OrI = Or;
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if (Op1User) {
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if (Or->getOperand(0) == OpUser)
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*Op1User = dyn_cast<Instruction>(Or->getOperand(1));
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else
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*Op1User = dyn_cast<Instruction>(Or->getOperand(0));
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}
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Mask &= CI->getRawValue();
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return true;
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}
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}
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}
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}
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return false;
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}
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/// isInsertShiftHalf - Helper function for emitBitfieldInsert. Returns true if
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/// OpUser has one use, is used by an or instruction, and is itself a shift
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/// instruction that is either used directly by the or instruction, or is used
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/// by an and instruction whose second operand is a constant int, and which is
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/// used by the or instruction.
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static bool isInsertShiftHalf(User *OpUser, Instruction **Op1User,
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Instruction **OrI, Instruction **OptAndI,
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unsigned &Shift, unsigned &Mask) {
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// If this instruction doesn't have one use, then return false.
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if (!OpUser->hasOneUse())
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return false;
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Mask = 0xFFFFFFFF;
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if (ShiftInst *SI = dyn_cast<ShiftInst>(OpUser)) {
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if (ConstantInt *CI = dyn_cast<ConstantInt>(SI->getOperand(1))) {
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Shift = CI->getRawValue();
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if (SI->getOpcode() == Instruction::Shl)
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Mask <<= Shift;
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else if (!SI->getOperand(0)->getType()->isSigned()) {
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Mask >>= Shift;
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Shift = 32 - Shift;
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}
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// Now check to see if the shift instruction is used by an or.
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Value *ShiftUse = *(OpUser->use_begin());
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Value *OptAndICopy = 0;
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if (BinaryOperator *BO = dyn_cast<BinaryOperator>(ShiftUse)) {
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if (BO->getOpcode() == Instruction::And && BO->hasOneUse()) {
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if (ConstantInt *ACI = dyn_cast<ConstantInt>(BO->getOperand(1))) {
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if (OptAndI) *OptAndI = BO;
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OptAndICopy = BO;
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Mask &= ACI->getRawValue();
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BO = dyn_cast<BinaryOperator>(*(BO->use_begin()));
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}
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}
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if (BO && BO->getOpcode() == Instruction::Or) {
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if (OrI) *OrI = BO;
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if (Op1User) {
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if (BO->getOperand(0) == OpUser || BO->getOperand(0) == OptAndICopy)
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*Op1User = dyn_cast<Instruction>(BO->getOperand(1));
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else
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*Op1User = dyn_cast<Instruction>(BO->getOperand(0));
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}
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return true;
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}
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}
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}
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}
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return false;
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}
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/// emitBitfieldInsert - turn a shift used only by an and with immediate into
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/// the rotate left word immediate then mask insert (rlwimi) instruction.
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/// Patterns matched:
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/// 1. or shl, and 5. or (shl-and), and 9. or and, and
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/// 2. or and, shl 6. or and, (shl-and)
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/// 3. or shr, and 7. or (shr-and), and
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/// 4. or and, shr 8. or and, (shr-and)
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bool PPC32ISel::emitBitfieldInsert(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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User *OpUser, unsigned DestReg) {
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// Instructions to skip if we match any of the patterns
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Instruction *Op0User, *Op1User = 0, *OptAndI = 0, *OrI = 0;
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unsigned TgtMask, InsMask, Amount = 0;
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bool matched = false;
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// We require OpUser to be an instruction to continue
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Op0User = dyn_cast<Instruction>(OpUser);
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if (0 == Op0User)
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return false;
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// Look for cases 2, 4, 6, 8, and 9
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if (isInsertAndHalf(Op0User, &Op1User, &OrI, TgtMask))
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if (Op1User)
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if (isInsertAndHalf(Op1User, 0, 0, InsMask))
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matched = true;
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else if (isInsertShiftHalf(Op1User, 0, 0, &OptAndI, Amount, InsMask))
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matched = true;
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// Look for cases 1, 3, 5, and 7. Force the shift argument to be the one
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// inserted into the target, since rlwimi can only rotate the value inserted,
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// not the value being inserted into.
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if (matched == false)
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if (isInsertShiftHalf(Op0User, &Op1User, &OrI, &OptAndI, Amount, InsMask))
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if (Op1User && isInsertAndHalf(Op1User, 0, 0, TgtMask)) {
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std::swap(Op0User, Op1User);
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matched = true;
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}
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// We didn't succeed in matching one of the patterns, so return false
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if (matched == false)
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return false;
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// If the masks xor to -1, and the insert mask is a run of ones, then we have
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// succeeded in matching one of the cases for generating rlwimi. Update the
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// skip lists and users of the Instruction::Or.
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unsigned MB, ME;
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if (((TgtMask ^ InsMask) == 0xFFFFFFFF) && isRunOfOnes(InsMask, MB, ME)) {
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SkipList.push_back(Op0User);
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SkipList.push_back(Op1User);
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SkipList.push_back(OptAndI);
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InsertMap[OrI] = RlwimiRec(Op0User->getOperand(0), Op1User->getOperand(0),
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Amount, MB, ME);
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return true;
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}
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return false;
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}
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/// emitBitfieldExtract - turn a shift used only by an and with immediate into the
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/// rotate left word immediate then and with mask (rlwinm) instruction.
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bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator IP,
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BinaryOperator *BO, Value *Op,
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unsigned Amount, bool isLeftShift,
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unsigned DestReg) {
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return false;
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if (BO && BO->getOpcode() == Instruction::And) {
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// Since the powerpc shift instructions are really rotate left, subtract 32
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// to simulate a right shift.
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unsigned Rotate = (isLeftShift) ? Amount : 32 - Amount;
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if (ConstantInt *CI = dyn_cast<ConstantInt>(BO->getOperand(1))) {
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unsigned Imm = CI->getRawValue(), MB, ME;
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// In the case of a left shift or unsigned right shift, be sure to clear
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// any bits that would have been zeroes shifted in from the left or right.
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// Usually instcombine will do this for us, but there's no guarantee the
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// optimization has been performed already.
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//
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// Also, take this opportunity to check for the algebraic right shift case
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// where the mask would overlap sign bits shifted in from the left. We do
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// not want to perform the optimization in that case since we could clear
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// bits that should be set. Think of int (x >> 17) & 0x0000FFFF;
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unsigned mask = 0xFFFFFFFF;
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if (isLeftShift)
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Imm &= (mask << Amount);
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else if (!isLeftShift && !Op->getType()->isSigned())
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Imm &= (mask >> Amount);
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else if (((mask << Rotate) & Imm) != 0)
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return false;
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if (isRunOfOnes(Imm, MB, ME)) {
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unsigned SrcReg = getReg(Op, MBB, IP);
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BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
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.addImm(Rotate).addImm(MB).addImm(ME);
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BO->replaceAllUsesWith(Op->use_back());
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SkipList.push_back(BO);
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return true;
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}
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}
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}
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return false;
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}
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@ -2322,9 +2467,9 @@ void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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// Special case: op Reg, <const int>
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1))
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if (Class != cLong) {
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if (OperatorClass == 2 && emitBitfieldInsert(BO, 0, Op0))
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if (emitBitfieldInsert(MBB, IP, BO, DestReg))
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return;
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unsigned Op0r = getReg(Op0, MBB, IP);
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emitBinaryConstOperation(MBB, IP, Op0r, CI, OperatorClass, DestReg);
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return;
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@ -2619,6 +2764,9 @@ void PPC32ISel::emitDivRemOperation(MachineBasicBlock *MBB,
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/// because the shift amount has to be in CL, not just any old register.
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///
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void PPC32ISel::visitShiftInst(ShiftInst &I) {
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if (std::find(SkipList.begin(), SkipList.end(), &I) != SkipList.end())
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return;
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MachineBasicBlock::iterator IP = BB->end();
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emitShiftOperation(BB, IP, I.getOperand(0), I.getOperand(1),
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I.getOpcode() == Instruction::Shl, I.getType(),
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@ -2776,17 +2924,16 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
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assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
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unsigned Amount = CUI->getValue();
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// If this is a left shift with one use, and that use is an And instruction,
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// then attempt to emit a bitfield insert.
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if (isLeftShift) {
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User *U = Op->use_back();
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if (U->hasOneUse()) {
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Value *V = *(U->use_begin());
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BinaryOperator *BO = dyn_cast<BinaryOperator>(V);
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if (BO && BO->getOpcode() == Instruction::And) {
|
||||
if (emitBitfieldInsert(BO, Amount, Op))
|
||||
return;
|
||||
}
|
||||
// If this is a shift with one use, and that use is an And instruction,
|
||||
// then attempt to emit a bitfield operation.
|
||||
User *U = Op->use_back();
|
||||
if (U->hasOneUse()) {
|
||||
BinaryOperator *BO = dyn_cast<BinaryOperator>(*(U->use_begin()));
|
||||
if (BO) {
|
||||
if (emitBitfieldInsert(MBB, IP, U, DestReg))
|
||||
return;
|
||||
if (emitBitfieldExtract(MBB, IP, BO, Op, Amount, isLeftShift, DestReg))
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user