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R600/SI: Only select cvt_flr/cvt_rpi with no NaNs.

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These have different behavior from cvt_i32_f32 on NaN.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227693 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2015-01-31 21:28:13 +00:00
parent 7708f5b68a
commit 9061eb6d2e
3 changed files with 31 additions and 17 deletions
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6
lib/Target/R600/AMDGPUInstructions.td
View File

@ -612,12 +612,14 @@ def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
def cvt_rpi_i32_f32 : PatFrag <
(ops node:$src),
(fp_to_sint (ffloor (fadd $src, FP_HALF)))
(fp_to_sint (ffloor (fadd $src, FP_HALF))),
[{ (void) N; return TM.Options.NoNaNsFPMath; }]
>;
def cvt_flr_i32_f32 : PatFrag <
(ops node:$src),
(fp_to_sint (ffloor $src))
(fp_to_sint (ffloor $src)),
[{ (void)N; return TM.Options.NoNaNsFPMath; }]
>;
/*

20
test/CodeGen/R600/cvt_flr_i32_f32.ll
View File

@ -1,12 +1,14 @@
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=SI -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.fabs.f32(float) #1
declare float @llvm.floor.f32(float) #1
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_0:
; SI-SAFE-NOT: v_cvt_flr_i32_f32
; SI-NOT: add
; SI: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
; SI: s_endpgm
define void @cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
%floor = call float @llvm.floor.f32(float %x) #1
@ -17,7 +19,8 @@ define void @cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_1:
; SI: v_add_f32_e64 [[TMP:v[0-9]+]], 1.0, s{{[0-9]+}}
; SI: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]]
; SI-SAFE-NOT: v_cvt_flr_i32_f32
; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]]
; SI: s_endpgm
define void @cvt_flr_i32_f32_1(i32 addrspace(1)* %out, float %x) #0 {
%fadd = fadd float %x, 1.0
@ -29,7 +32,8 @@ define void @cvt_flr_i32_f32_1(i32 addrspace(1)* %out, float %x) #0 {
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs:
; SI-NOT: add
; SI: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
; SI-SAFE-NOT: v_cvt_flr_i32_f32
; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
; SI: s_endpgm
define void @cvt_flr_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
%x.fabs = call float @llvm.fabs.f32(float %x) #1
@ -41,7 +45,8 @@ define void @cvt_flr_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fneg:
; SI-NOT: add
; SI: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
; SI-SAFE-NOT: v_cvt_flr_i32_f32
; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
; SI: s_endpgm
define void @cvt_flr_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
%x.fneg = fsub float -0.000000e+00, %x
@ -53,7 +58,8 @@ define void @cvt_flr_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs_fneg:
; SI-NOT: add
; SI: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
; SI-SAFE-NOT: v_cvt_flr_i32_f32
; SI-NONAN: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
; SI: s_endpgm
define void @cvt_flr_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
%x.fabs = call float @llvm.fabs.f32(float %x) #1

22
test/CodeGen/R600/cvt_rpi_i32_f32.ll
View File

@ -1,11 +1,13 @@
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=SI -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.fabs.f32(float) #1
declare float @llvm.floor.f32(float) #1
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32:
; SI: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
; SI-SAFE-NOT: v_cvt_rpi_i32_f32
; SI-NONAN: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
; SI: s_endpgm
define void @cvt_rpi_i32_f32(i32 addrspace(1)* %out, float %x) #0 {
%fadd = fadd float %x, 0.5
@ -16,7 +18,8 @@ define void @cvt_rpi_i32_f32(i32 addrspace(1)* %out, float %x) #0 {
}
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs:
; SI: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
; SI-SAFE-NOT: v_cvt_rpi_i32_f32
; SI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
; SI: s_endpgm
define void @cvt_rpi_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
%x.fabs = call float @llvm.fabs.f32(float %x) #1
@ -29,9 +32,10 @@ define void @cvt_rpi_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
; FIXME: This doesn't work because it forms fsub 0.5, x
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fneg:
; XSI: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, s{{[0-9]+}}
; SI: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
; SI-SAFE-NOT: v_cvt_flr_i32_f32
; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
; SI: s_endpgm
define void @cvt_rpi_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
%x.fneg = fsub float -0.000000e+00, %x
@ -44,10 +48,12 @@ define void @cvt_rpi_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
; FIXME: This doesn't work for same reason as above
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs_fneg:
; XSI: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
; SI-SAFE-NOT: v_cvt_rpi_i32_f32
; XSI-NONAN: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, |s{{[0-9]+}}|
; SI: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
; SI-SAFE-NOT: v_cvt_flr_i32_f32
; SI-NONAN: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
; SI: s_endpgm
define void @cvt_rpi_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
%x.fabs = call float @llvm.fabs.f32(float %x) #1