From 9068d5310cfafdd201f77b0434dc7eebb7f51a45 Mon Sep 17 00:00:00 2001
From: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Date: Mon, 24 Jun 2013 11:02:38 +0000
Subject: [PATCH] [PowerPC] Support bd(n)zl and bd(n)zlrl

This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184720 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCInstrInfo.td   | 12 ++++++++++++
 test/MC/PowerPC/ppc64-encoding-ext.s | 14 ++++++++++----
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 8f896ad7a2e..700875a0830 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -938,6 +938,18 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
     def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
                             "b${cond:cc}lrl ${cond:reg}", BrB, []>;
   }
+  let Defs = [CTR], Uses = [CTR, RM] in {
+    def BDZL  : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
+                        "bdzl $dst">;
+    def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
+                        "bdnzl $dst">;
+  }
+  let Defs = [CTR], Uses = [CTR, LR, RM] in {
+    def BDZLRL  : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
+                               "bdzlrl", BrB, []>;
+    def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
+                               "bdnzlrl", BrB, []>;
+  }
 }
 
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
diff --git a/test/MC/PowerPC/ppc64-encoding-ext.s b/test/MC/PowerPC/ppc64-encoding-ext.s
index 31525c77719..9ca8199de9d 100644
--- a/test/MC/PowerPC/ppc64-encoding-ext.s
+++ b/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -54,9 +54,12 @@
 # FIXME: bdnza target
 # CHECK: bdnzlr                          # encoding: [0x4e,0x00,0x00,0x20]
          bdnzlr
-# FIXME: bdnzl target
+# CHECK: bdnzl target                    # encoding: [0x42,0x00,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdnzl target
 # FIXME: bdnzla target
-# FIXME: bdnzlrl
+# CHECK: bdnzlrl                         # encoding: [0x4e,0x00,0x00,0x21]
+         bdnzlrl
 
 # FIXME: bdnzt 2, target
 # FIXME: bdnzt target
@@ -89,9 +92,12 @@
 # FIXME: bdza target
 # CHECK: bdzlr                           # encoding: [0x4e,0x40,0x00,0x20]
          bdzlr
-# FIXME: bdzl target
+# CHECK: bdzl target                     # encoding: [0x42,0x40,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdzl target
 # FIXME: bdzla target
-# FIXME: bdzlrl
+# CHECK: bdzlrl                          # encoding: [0x4e,0x40,0x00,0x21]
+         bdzlrl
 
 # FIXME: bdzt 2, target
 # FIXME: bdzt target