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T2 Load/Store Multiple:

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These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-24 21:36:56 +00:00
parent 83ccbff84f
commit 9091bf25d9
2 changed files with 4 additions and 1 deletions
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2
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@ -1140,7 +1140,7 @@ static bool DisassembleThumb2LdStMul(MCInst &MI, unsigned Opcode, uint32_t insn,
Opcode == ARM::t2STMIA || Opcode == ARM::t2STMIA_UPD ||
Opcode == ARM::t2STMDB || Opcode == ARM::t2STMDB_UPD)
&& "Unexpected opcode");
assert(NumOps >= 5 && "Thumb2 LdStMul expects NumOps >= 5");
assert(NumOps >= 4 && "Thumb2 LdStMul expects NumOps >= 4");
NumOpsAdded = 0;

3
test/MC/Disassembler/ARM/thumb-tests.txt
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@ -136,3 +136,6 @@
# CHECK: vcmpe.f64 d8, #0
0xb5 0xee 0xc0 0x8b
# CHECK: stmdb.w sp, {r0, r2, r3, r8, r11, lr}
0x0d 0xe9 0x0d 0x49