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Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
91d2cc9cdd
commit
909652f687
@ -104,6 +104,8 @@ def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
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"Support 16-bit floating point conversion instructions">;
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def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
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"Support LZCNT instruction">;
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def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
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"Support BMI instructions">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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@ -158,6 +160,12 @@ def : Proc<"core-avx-i", [FeatureSSE42, FeatureCMPXCHG16B,
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FeatureAES, FeatureCLMUL,
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FeatureRDRAND, FeatureF16C]>;
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// Haswell
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def : Proc<"core-avx2", [FeatureSSE42, FeatureCMPXCHG16B, FeatureAES,
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FeatureCLMUL, FeatureRDRAND, FeatureF16C,
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FeatureFMA3, FeatureMOVBE, FeatureLZCNT,
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FeatureBMI]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [Feature3DNow]>;
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def : Proc<"k6-3", [Feature3DNow]>;
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@ -379,11 +379,15 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::FREM , MVT::f80 , Expand);
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setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
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setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
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if (Subtarget->is64Bit())
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setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
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if (Subtarget->hasBMI()) {
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setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
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} else {
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setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
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if (Subtarget->is64Bit())
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setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
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}
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if (Subtarget->hasLZCNT()) {
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setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
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@ -478,6 +478,7 @@ def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
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def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
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def HasF16C : Predicate<"Subtarget->hasF16C()">;
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def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
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def HasBMI : Predicate<"Subtarget->hasBMI()">;
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def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
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def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
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def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
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@ -1372,6 +1373,37 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
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(implicit EFLAGS)]>, XS;
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}
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//===----------------------------------------------------------------------===//
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// TZCNT Instruction
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//
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let Predicates = [HasBMI], Defs = [EFLAGS] in {
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def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"tzcnt{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
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OpSize;
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def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"tzcnt{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (cttz (loadi16 addr:$src))),
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(implicit EFLAGS)]>, XS, OpSize;
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def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"tzcnt{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;
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def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"tzcnt{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (cttz (loadi32 addr:$src))),
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(implicit EFLAGS)]>, XS;
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def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"tzcnt{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
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XS;
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def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"tzcnt{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (cttz (loadi64 addr:$src))),
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(implicit EFLAGS)]>, XS;
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}
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//===----------------------------------------------------------------------===//
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// Subsystems.
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//===----------------------------------------------------------------------===//
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@ -290,6 +290,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
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, HasRDRAND(false)
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, HasF16C(false)
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, HasLZCNT(false)
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, HasBMI(false)
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, IsBTMemSlow(false)
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, IsUAMemFast(false)
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, HasVectorUAMem(false)
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@ -102,6 +102,9 @@ protected:
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/// HasLZCNT - Processor has LZCNT instruction.
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bool HasLZCNT;
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/// HasBMI - Processor has BMI1 instructions.
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bool HasBMI;
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/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
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bool IsBTMemSlow;
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@ -188,6 +191,7 @@ public:
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bool hasRDRAND() const { return HasRDRAND; }
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bool hasF16C() const { return HasF16C; }
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bool hasLZCNT() const { return HasLZCNT; }
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bool hasBMI() const { return HasBMI; }
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bool isBTMemSlow() const { return IsBTMemSlow; }
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bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
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bool hasVectorUAMem() const { return HasVectorUAMem; }
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38
test/CodeGen/X86/bmi.ll
Normal file
38
test/CodeGen/X86/bmi.ll
Normal file
@ -0,0 +1,38 @@
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; RUN: llc < %s -march=x86-64 -mattr=+bmi | FileCheck %s
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define i32 @t1(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x )
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ret i32 %tmp
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; CHECK: t1:
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; CHECK: tzcntl
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}
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declare i32 @llvm.cttz.i32(i32) nounwind readnone
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define i16 @t2(i16 %x) nounwind {
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%tmp = tail call i16 @llvm.cttz.i16( i16 %x )
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ret i16 %tmp
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; CHECK: t2:
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; CHECK: tzcntw
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}
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declare i16 @llvm.cttz.i16(i16) nounwind readnone
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define i64 @t3(i64 %x) nounwind {
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%tmp = tail call i64 @llvm.cttz.i64( i64 %x )
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ret i64 %tmp
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; CHECK: t3:
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; CHECK: tzcntq
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}
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declare i64 @llvm.cttz.i64(i64) nounwind readnone
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define i8 @t4(i8 %x) nounwind {
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%tmp = tail call i8 @llvm.cttz.i8( i8 %x )
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ret i8 %tmp
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; CHECK: t4:
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; CHECK: tzcntw
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}
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declare i8 @llvm.cttz.i8(i8) nounwind readnone
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@ -497,3 +497,12 @@
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# CHECK: lzcntq %rax, %rax
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0xf3 0x48 0x0f 0xbd 0xc0
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# CHECK: tzcntl %eax, %eax
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0xf3 0x0f 0xbc 0xc0
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# CHECK: tzcntw %ax, %ax
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0x66 0xf3 0x0f 0xbc 0xc0
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# CHECK: tzcntq %rax, %rax
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0xf3 0x48 0x0f 0xbc 0xc0
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@ -477,3 +477,9 @@
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# CHECK: lzcntw %ax, %ax
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0x66 0xf3 0x0f 0xbd 0xc0
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# CHECK: tzcntl %eax, %eax
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0xf3 0x0f 0xbc 0xc0
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# CHECK: tzcntw %ax, %ax
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0x66 0xf3 0x0f 0xbc 0xc0
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