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[x86] Fix the completely broken vector widening legalization of bswap.

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This operation was classified as a binary operation in the widening
logic for some reason (clearly, untested). It is in fact a unary
operation. Add a RUN line to a test to exercise this for x86.

Note that again the vector widening strategy doesn't regress anything
and in one case removes a totally unecessary instruction that we
couldn't avoid when promoting the element type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212257 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2014-07-03 07:04:38 +00:00
parent 7e924a68b5
commit 90ac572331
2 changed files with 30 additions and 1 deletions
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2
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -1549,7 +1549,6 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
case ISD::ADD:
case ISD::AND:
case ISD::BSWAP:
case ISD::MUL:
case ISD::MULHS:
case ISD::MULHU:
@ -1596,6 +1595,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
Res = WidenVecRes_Convert(N);
break;
case ISD::BSWAP:
case ISD::CTLZ:
case ISD::CTPOP:
case ISD::CTTZ:

29
test/CodeGen/X86/bswap-vector.ll
View File

@ -1,6 +1,7 @@
; RUN: llc < %s -mcpu=x86-64 | FileCheck %s -check-prefix=CHECK-NOSSSE3
; RUN: llc < %s -mcpu=core2 | FileCheck %s -check-prefix=CHECK-SSSE3
; RUN: llc < %s -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK-AVX2
; RUN: llc < %s -mcpu=core-avx2 -x86-experimental-vector-widening-legalization | FileCheck %s -check-prefix=CHECK-WIDE-AVX2
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
@ -31,6 +32,10 @@ entry:
; CHECK-AVX2-LABEL: @test1
; CHECK-AVX2: vpshufb
; CHECK-AVX2-NEXT: retq
; CHECK-WIDE-AVX2-LABEL: @test1
; CHECK-WIDE-AVX2: vpshufb
; CHECK-WIDE-AVX2-NEXT: retq
}
define <4 x i32> @test2(<4 x i32> %v) #0 {
@ -52,6 +57,10 @@ entry:
; CHECK-AVX2-LABEL: @test2
; CHECK-AVX2: vpshufb
; CHECK-AVX2-NEXT: retq
; CHECK-WIDE-AVX2-LABEL: @test2
; CHECK-WIDE-AVX2: vpshufb
; CHECK-WIDE-AVX2-NEXT: retq
}
define <2 x i64> @test3(<2 x i64> %v) #0 {
@ -71,6 +80,10 @@ entry:
; CHECK-AVX2-LABEL: @test3
; CHECK-AVX2: vpshufb
; CHECK-AVX2-NEXT: retq
; CHECK-WIDE-AVX2-LABEL: @test3
; CHECK-WIDE-AVX2: vpshufb
; CHECK-WIDE-AVX2-NEXT: retq
}
declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
@ -90,6 +103,10 @@ entry:
; CHECK-AVX2-LABEL: @test4
; CHECK-AVX2: vpshufb
; CHECK-AVX2-NEXT: retq
; CHECK-WIDE-AVX2-LABEL: @test4
; CHECK-WIDE-AVX2: vpshufb
; CHECK-WIDE-AVX2-NEXT: retq
}
define <8 x i32> @test5(<8 x i32> %v) #0 {
@ -105,6 +122,10 @@ entry:
; CHECK-AVX2-LABEL: @test5
; CHECK-AVX2: vpshufb
; CHECK-AVX2-NEXT: retq
; CHECK-WIDE-AVX2-LABEL: @test5
; CHECK-WIDE-AVX2: vpshufb
; CHECK-WIDE-AVX2-NEXT: retq
}
define <4 x i64> @test6(<4 x i64> %v) #0 {
@ -120,6 +141,10 @@ entry:
; CHECK-AVX2-LABEL: @test6
; CHECK-AVX2: vpshufb
; CHECK-AVX2-NEXT: retq
; CHECK-WIDE-AVX2-LABEL: @test6
; CHECK-WIDE-AVX2: vpshufb
; CHECK-WIDE-AVX2-NEXT: retq
}
declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
@ -138,6 +163,10 @@ entry:
; CHECK-AVX2: vpshufb
; CHECK-AVX2: vpsrld $16
; CHECK-AVX2-NEXT: retq
; CHECK-WIDE-AVX2-LABEL: @test7
; CHECK-WIDE-AVX2: vpshufb
; CHECK-WIDE-AVX2-NEXT: retq
}
attributes #0 = { nounwind uwtable }