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MC/X86: We now match instructions like "incl %eax" correctly for the arch we are

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assembling; remove crufty custom cleanup code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108681 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Dunbar 2010-07-19 06:14:54 +00:00
parent cf246b7f0b
commit 90b374cded
3 changed files with 3 additions and 57 deletions
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53
lib/Target/X86/AsmParser/X86AsmParser.cpp
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@ -50,8 +50,6 @@ private:
bool ParseDirectiveWord(unsigned Size, SMLoc L);
void InstructionCleanup(MCInst &Inst);
bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCInst &Inst);
@ -840,57 +838,6 @@ bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
return false;
}
/// LowerMOffset - Lower an 'moffset' form of an instruction, which just has a
/// imm operand, to having "rm" or "mr" operands with the offset in the disp
/// field.
static void LowerMOffset(MCInst &Inst, unsigned Opc, unsigned RegNo,
bool isMR) {
MCOperand Disp = Inst.getOperand(0);
// Start over with an empty instruction.
Inst = MCInst();
Inst.setOpcode(Opc);
if (!isMR)
Inst.addOperand(MCOperand::CreateReg(RegNo));
// Add the mem operand.
Inst.addOperand(MCOperand::CreateReg(0)); // Segment
Inst.addOperand(MCOperand::CreateImm(1)); // Scale
Inst.addOperand(MCOperand::CreateReg(0)); // IndexReg
Inst.addOperand(Disp); // Displacement
Inst.addOperand(MCOperand::CreateReg(0)); // BaseReg
if (isMR)
Inst.addOperand(MCOperand::CreateReg(RegNo));
}
// FIXME: Custom X86 cleanup function to implement a temporary hack to handle
// matching INCL/DECL correctly for x86_64. This needs to be replaced by a
// proper mechanism for supporting (ambiguous) feature dependent instructions.
void X86ATTAsmParser::InstructionCleanup(MCInst &Inst) {
if (!Is64Bit) return;
switch (Inst.getOpcode()) {
case X86::DEC16r: Inst.setOpcode(X86::DEC64_16r); break;
case X86::DEC16m: Inst.setOpcode(X86::DEC64_16m); break;
case X86::DEC32r: Inst.setOpcode(X86::DEC64_32r); break;
case X86::DEC32m: Inst.setOpcode(X86::DEC64_32m); break;
case X86::INC16r: Inst.setOpcode(X86::INC64_16r); break;
case X86::INC16m: Inst.setOpcode(X86::INC64_16m); break;
case X86::INC32r: Inst.setOpcode(X86::INC64_32r); break;
case X86::INC32m: Inst.setOpcode(X86::INC64_32m); break;
// moffset instructions are x86-32 only.
case X86::MOV8o8a: LowerMOffset(Inst, X86::MOV8rm , X86::AL , false); break;
case X86::MOV16o16a: LowerMOffset(Inst, X86::MOV16rm, X86::AX , false); break;
case X86::MOV32o32a: LowerMOffset(Inst, X86::MOV32rm, X86::EAX, false); break;
case X86::MOV8ao8: LowerMOffset(Inst, X86::MOV8mr , X86::AL , true); break;
case X86::MOV16ao16: LowerMOffset(Inst, X86::MOV16mr, X86::AX , true); break;
case X86::MOV32ao32: LowerMOffset(Inst, X86::MOV32mr, X86::EAX, true); break;
}
}
bool
X86ATTAsmParser::MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*>
&Operands,

1
lib/Target/X86/X86.td
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@ -180,7 +180,6 @@ include "X86CallingConv.td"
// Currently the X86 assembly parser only supports ATT syntax.
def ATTAsmParser : AsmParser {
string AsmParserClassName = "ATTAsmParser";
string AsmParserInstCleanup = "InstructionCleanup";
string MatchInstructionName = "MatchInstructionImpl";
int Variant = 0;

6
test/MC/AsmParser/X86/x86_64-new-encoder.s
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@ -72,9 +72,9 @@ stosl
// Not moffset forms of moves, they are x86-32 only! rdar://7947184
movb 0, %al // CHECK: movb 0, %al # encoding: [0x8a,0x04,0x25,A,A,A,A]
movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0x8b,0x04,0x25,A,A,A,A]
movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,A,A,A,A]
movb 0, %al // CHECK: movb 0, %al # encoding: [0x8a,0x04,0x25,0x00,0x00,0x00,0x00]
movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
// CHECK: pushfq # encoding: [0x9c]
pushf