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MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
assembling; remove crufty custom cleanup code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108681 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -50,8 +50,6 @@ private:
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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void InstructionCleanup(MCInst &Inst);
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bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCInst &Inst);
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@ -840,57 +838,6 @@ bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
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return false;
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}
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/// LowerMOffset - Lower an 'moffset' form of an instruction, which just has a
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/// imm operand, to having "rm" or "mr" operands with the offset in the disp
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/// field.
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static void LowerMOffset(MCInst &Inst, unsigned Opc, unsigned RegNo,
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bool isMR) {
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MCOperand Disp = Inst.getOperand(0);
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// Start over with an empty instruction.
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Inst = MCInst();
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Inst.setOpcode(Opc);
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if (!isMR)
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Inst.addOperand(MCOperand::CreateReg(RegNo));
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// Add the mem operand.
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Inst.addOperand(MCOperand::CreateReg(0)); // Segment
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Inst.addOperand(MCOperand::CreateImm(1)); // Scale
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Inst.addOperand(MCOperand::CreateReg(0)); // IndexReg
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Inst.addOperand(Disp); // Displacement
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Inst.addOperand(MCOperand::CreateReg(0)); // BaseReg
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if (isMR)
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Inst.addOperand(MCOperand::CreateReg(RegNo));
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}
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// FIXME: Custom X86 cleanup function to implement a temporary hack to handle
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// matching INCL/DECL correctly for x86_64. This needs to be replaced by a
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// proper mechanism for supporting (ambiguous) feature dependent instructions.
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void X86ATTAsmParser::InstructionCleanup(MCInst &Inst) {
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if (!Is64Bit) return;
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switch (Inst.getOpcode()) {
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case X86::DEC16r: Inst.setOpcode(X86::DEC64_16r); break;
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case X86::DEC16m: Inst.setOpcode(X86::DEC64_16m); break;
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case X86::DEC32r: Inst.setOpcode(X86::DEC64_32r); break;
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case X86::DEC32m: Inst.setOpcode(X86::DEC64_32m); break;
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case X86::INC16r: Inst.setOpcode(X86::INC64_16r); break;
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case X86::INC16m: Inst.setOpcode(X86::INC64_16m); break;
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case X86::INC32r: Inst.setOpcode(X86::INC64_32r); break;
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case X86::INC32m: Inst.setOpcode(X86::INC64_32m); break;
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// moffset instructions are x86-32 only.
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case X86::MOV8o8a: LowerMOffset(Inst, X86::MOV8rm , X86::AL , false); break;
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case X86::MOV16o16a: LowerMOffset(Inst, X86::MOV16rm, X86::AX , false); break;
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case X86::MOV32o32a: LowerMOffset(Inst, X86::MOV32rm, X86::EAX, false); break;
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case X86::MOV8ao8: LowerMOffset(Inst, X86::MOV8mr , X86::AL , true); break;
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case X86::MOV16ao16: LowerMOffset(Inst, X86::MOV16mr, X86::AX , true); break;
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case X86::MOV32ao32: LowerMOffset(Inst, X86::MOV32mr, X86::EAX, true); break;
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}
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}
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bool
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X86ATTAsmParser::MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*>
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&Operands,
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@ -180,7 +180,6 @@ include "X86CallingConv.td"
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// Currently the X86 assembly parser only supports ATT syntax.
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def ATTAsmParser : AsmParser {
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string AsmParserClassName = "ATTAsmParser";
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string AsmParserInstCleanup = "InstructionCleanup";
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string MatchInstructionName = "MatchInstructionImpl";
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int Variant = 0;
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@ -72,9 +72,9 @@ stosl
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// Not moffset forms of moves, they are x86-32 only! rdar://7947184
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movb 0, %al // CHECK: movb 0, %al # encoding: [0x8a,0x04,0x25,A,A,A,A]
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movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0x8b,0x04,0x25,A,A,A,A]
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movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,A,A,A,A]
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movb 0, %al // CHECK: movb 0, %al # encoding: [0x8a,0x04,0x25,0x00,0x00,0x00,0x00]
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movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
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movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,0x00,0x00,0x00,0x00]
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// CHECK: pushfq # encoding: [0x9c]
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pushf
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