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When combining consecutive stores allow loads in between the stores, if the loads do not alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168832 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -291,6 +291,10 @@ namespace {
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unsigned SrcValueAlign2,
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const MDNode *TBAAInfo2) const;
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/// isAlias - Return true if there is any possibility that the two addresses
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/// overlap.
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bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1);
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/// FindAliasInfo - Extracts the relevant alias information from the memory
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/// node. Returns true if the operand was a load.
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bool FindAliasInfo(SDNode *N,
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@ -7552,7 +7556,14 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
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if (BasePtr.first.getOpcode() == ISD::UNDEF)
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return false;
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// Save the LoadSDNodes that we find in the chain.
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// We need to make sure that these nodes do not interfere with
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// any of the store nodes.
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SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
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// Save the StoreSDNodes that we find in the chain.
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SmallVector<MemOpLink, 8> StoreNodes;
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// Walk up the chain and look for nodes with offsets from the same
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// base pointer. Stop when reaching an instruction with a different kind
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// or instruction which has a different base pointer.
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@ -7596,8 +7607,26 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
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// We found a potential memory operand to merge.
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StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++));
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// Move up the chain to the next memory operation.
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Index = dyn_cast<StoreSDNode>(Index->getChain().getNode());
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// Find the next memory operand in the chain. If the next operand in the
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// chain is a store then move up and continue the scan with the next
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// memory operand. If the next operand is a load save it and use alias
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// information to check if it interferes with anything.
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SDNode *NextInChain = Index->getChain().getNode();
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while (1) {
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if (isa<StoreSDNode>(NextInChain)) {
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// We found a store node. Use it for the next iteration.
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Index = cast<StoreSDNode>(NextInChain);
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break;
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} else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
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// Save the load node for later. Continue the scan.
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AliasLoadNodes.push_back(Ldn);
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NextInChain = Ldn->getChain().getNode();
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continue;
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} else {
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Index = NULL;
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break;
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}
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}
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}
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// Check if there is anything to merge.
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@ -7612,11 +7641,23 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
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// store memory address.
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unsigned LastConsecutiveStore = 0;
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int64_t StartAddress = StoreNodes[0].OffsetFromBase;
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for (unsigned i=1; i<StoreNodes.size(); ++i) {
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for (unsigned i = 1, e = StoreNodes.size(); i < e; ++i) {
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int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
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if (CurrAddress - StartAddress != (ElementSizeBytes * i))
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break;
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bool Alias = false;
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// Check if this store interferes with any of the loads that we found.
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for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
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if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
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Alias = true;
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break;
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}
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// We found a load that alias with this store. Stop the sequence.
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if (Alias)
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break;
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// Mark this node as useful.
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LastConsecutiveStore = i;
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}
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@ -9680,6 +9721,23 @@ bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
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return true;
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}
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bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) {
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SDValue Ptr0, Ptr1;
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int64_t Size0, Size1;
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const Value *SrcValue0, *SrcValue1;
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int SrcValueOffset0, SrcValueOffset1;
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unsigned SrcValueAlign0, SrcValueAlign1;
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const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1;
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FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0,
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SrcValueAlign0, SrcTBAAInfo0);
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FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1,
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SrcValueAlign1, SrcTBAAInfo1);
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return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0,
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SrcValueAlign0, SrcTBAAInfo0,
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Ptr1, Size1, SrcValue1, SrcValueOffset1,
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SrcValueAlign1, SrcTBAAInfo1);
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}
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/// FindAliasInfo - Extracts the relevant alias information from the memory
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/// node. Returns true if the operand was a load.
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bool DAGCombiner::FindAliasInfo(SDNode *N,
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52
test/CodeGen/X86/2012-11-28-merge-store-alias.ll
Normal file
52
test/CodeGen/X86/2012-11-28-merge-store-alias.ll
Normal file
@ -0,0 +1,52 @@
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; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win64 | FileCheck %s
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; CHECK: merge_stores_can
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; CHECK: callq foo
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: movups %xmm0
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; CHECK: callq foo
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; CHECK: ret
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declare i32 @foo([10 x i32]* )
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define i32 @merge_stores_can() nounwind ssp {
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%object1 = alloca [10 x i32]
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%ret0 = call i32 @foo([10 x i32]* %object1) nounwind
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%O1_1 = getelementptr [10 x i32]* %object1, i64 0, i32 1
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%O1_2 = getelementptr [10 x i32]* %object1, i64 0, i32 2
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%O1_3 = getelementptr [10 x i32]* %object1, i64 0, i32 3
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%O1_4 = getelementptr [10 x i32]* %object1, i64 0, i32 4
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%ld_ptr = getelementptr [10 x i32]* %object1, i64 0, i32 9
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store i32 0, i32* %O1_1
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store i32 0, i32* %O1_2
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%ret = load i32* %ld_ptr ; <--- does not alias.
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store i32 0, i32* %O1_3
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store i32 0, i32* %O1_4
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%ret1 = call i32 @foo([10 x i32]* %object1) nounwind
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ret i32 %ret
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}
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; CHECK: merge_stores_cant
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; CHECK-NOT: xorps %xmm0, %xmm0
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; CHECK-NOT: movups %xmm0
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; CHECK: ret
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define i32 @merge_stores_cant([10 x i32]* %in0, [10 x i32]* %in1) nounwind ssp {
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%O1_1 = getelementptr [10 x i32]* %in1, i64 0, i32 1
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%O1_2 = getelementptr [10 x i32]* %in1, i64 0, i32 2
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%O1_3 = getelementptr [10 x i32]* %in1, i64 0, i32 3
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%O1_4 = getelementptr [10 x i32]* %in1, i64 0, i32 4
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%ld_ptr = getelementptr [10 x i32]* %in0, i64 0, i32 2
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store i32 0, i32* %O1_1
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store i32 0, i32* %O1_2
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%ret = load i32* %ld_ptr ; <--- may alias
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store i32 0, i32* %O1_3
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store i32 0, i32* %O1_4
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ret i32 %ret
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}
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