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InstCombine: Propagate exact for (sdiv -X, C) -> (sdiv X, -C)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222623 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Majnemer 2014-11-22 20:00:34 +00:00
parent 53a43d38df
commit 91349eecb0
2 changed files with 15 additions and 4 deletions
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10
lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
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@ -1082,10 +1082,12 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) {
return new ZExtInst(Builder->CreateICmpEQ(Op0, Op1), I.getType()); return new ZExtInst(Builder->CreateICmpEQ(Op0, Op1), I.getType());
// -X/C --> X/-C provided the negation doesn't overflow. // -X/C --> X/-C provided the negation doesn't overflow.
if (SubOperator *Sub = dyn_cast<SubOperator>(Op0)) Value *X;
if (match(Sub->getOperand(0), m_Zero()) && Sub->hasNoSignedWrap()) if (match(Op0, m_NSWSub(m_Zero(), m_Value(X)))) {
return BinaryOperator::CreateSDiv(Sub->getOperand(1), auto *BO = BinaryOperator::CreateSDiv(X, ConstantExpr::getNeg(RHS));
ConstantExpr::getNeg(RHS)); BO->setIsExact(I.isExact());
return BO;
}
} }
// If the sign bits of both operands are zero (i.e. we can prove they are // If the sign bits of both operands are zero (i.e. we can prove they are

9
test/Transforms/InstCombine/div.ll
View File

@ -295,3 +295,12 @@ define <2 x i64> @test33(<2 x i64> %x) nounwind {
; CHECK-NEXT: udiv exact <2 x i64> %x, <i64 192, i64 192> ; CHECK-NEXT: udiv exact <2 x i64> %x, <i64 192, i64 192>
; CHECK-NEXT: ret <2 x i64> ; CHECK-NEXT: ret <2 x i64>
} }
define <2 x i64> @test34(<2 x i64> %x) nounwind {
%neg = sub nsw <2 x i64> zeroinitializer, %x
%div = sdiv exact <2 x i64> %neg, <i64 3, i64 4>
ret <2 x i64> %div
; CHECK-LABEL: @test34(
; CHECK-NEXT: sdiv exact <2 x i64> %x, <i64 -3, i64 -4>
; CHECK-NEXT: ret <2 x i64>
}