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Pass "earlyclobber" bit through to machine
representation; coalescer and RA need to know about it. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56161 91177308-0d34-0410-b5e6-96231b3b80d8
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f5aeb1a8e4
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@ -68,6 +68,13 @@ private:
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/// This is only valid on definitions of registers.
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/// This is only valid on definitions of registers.
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bool IsDead : 1;
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bool IsDead : 1;
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/// IsEarlyClobber flag - this is only valid for MO_Register operands in
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/// an inline asm.
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/// IsEarlyClobber - True if this operand is marked earlyclobber in an
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/// inline asm. See gcc doc for description of earlyclobber.
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bool IsEarlyClobber : 1;
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/// SubReg - Subregister number, only valid for MO_Register. A value of 0
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/// SubReg - Subregister number, only valid for MO_Register. A value of 0
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/// indicates the MO_Register has no subReg.
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/// indicates the MO_Register has no subReg.
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unsigned char SubReg;
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unsigned char SubReg;
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@ -181,6 +188,11 @@ public:
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return IsKill;
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return IsKill;
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}
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}
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bool isEarlyClobber() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return IsEarlyClobber;
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}
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/// getNextOperandForReg - Return the next MachineOperand in the function that
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/// getNextOperandForReg - Return the next MachineOperand in the function that
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/// uses or defines this register.
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/// uses or defines this register.
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MachineOperand *getNextOperandForReg() const {
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MachineOperand *getNextOperandForReg() const {
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@ -226,6 +238,10 @@ public:
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IsDead = Val;
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IsDead = Val;
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}
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}
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void setIsEarlyClobber(bool Val = true) {
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assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
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IsEarlyClobber = Val;
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}
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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// Accessors for various operand types.
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// Accessors for various operand types.
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@ -311,7 +327,8 @@ public:
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/// the specified value. If an operand is known to be an register already,
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/// the specified value. If an operand is known to be an register already,
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/// the setReg method should be used.
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/// the setReg method should be used.
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void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
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void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
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bool isKill = false, bool isDead = false);
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bool isKill = false, bool isDead = false,
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bool isEarlyClobber = false);
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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// Construction methods.
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// Construction methods.
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@ -331,12 +348,14 @@ public:
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static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
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static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
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bool isKill = false, bool isDead = false,
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bool isKill = false, bool isDead = false,
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unsigned SubReg = 0) {
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unsigned SubReg = 0,
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bool isEarlyClobber = false) {
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MachineOperand Op(MachineOperand::MO_Register);
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MachineOperand Op(MachineOperand::MO_Register);
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Op.IsDef = isDef;
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Op.IsDef = isDef;
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Op.IsImp = isImp;
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Op.IsImp = isImp;
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Op.IsKill = isKill;
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Op.IsKill = isKill;
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Op.IsDead = isDead;
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Op.IsDead = isDead;
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Op.IsEarlyClobber = isEarlyClobber;
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Op.Contents.Reg.RegNo = Reg;
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Op.Contents.Reg.RegNo = Reg;
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Op.Contents.Reg.Prev = 0;
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Op.Contents.Reg.Prev = 0;
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Op.Contents.Reg.Next = 0;
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Op.Contents.Reg.Next = 0;
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@ -382,6 +401,7 @@ public:
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IsImp = MO.IsImp;
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IsImp = MO.IsImp;
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IsKill = MO.IsKill;
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IsKill = MO.IsKill;
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IsDead = MO.IsDead;
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IsDead = MO.IsDead;
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IsEarlyClobber = MO.IsEarlyClobber;
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SubReg = MO.SubReg;
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SubReg = MO.SubReg;
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ParentMI = MO.ParentMI;
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ParentMI = MO.ParentMI;
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Contents = MO.Contents;
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Contents = MO.Contents;
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@ -104,7 +104,8 @@ void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
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/// the specified value. If an operand is known to be an register already,
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/// the specified value. If an operand is known to be an register already,
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/// the setReg method should be used.
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/// the setReg method should be used.
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void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
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void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
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bool isKill, bool isDead) {
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bool isKill, bool isDead,
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bool isEarlyClobber) {
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// If this operand is already a register operand, use setReg to update the
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// If this operand is already a register operand, use setReg to update the
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// register's use/def lists.
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// register's use/def lists.
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if (isReg()) {
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if (isReg()) {
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@ -126,6 +127,7 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
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IsImp = isImp;
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IsImp = isImp;
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IsKill = isKill;
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IsKill = isKill;
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IsDead = isDead;
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IsDead = isDead;
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IsEarlyClobber = isEarlyClobber;
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SubReg = 0;
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SubReg = 0;
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}
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}
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@ -181,13 +183,15 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
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OS << "%mreg" << getReg();
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OS << "%mreg" << getReg();
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}
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}
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if (isDef() || isKill() || isDead() || isImplicit()) {
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if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
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OS << "<";
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OS << "<";
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bool NeedComma = false;
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bool NeedComma = false;
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if (isImplicit()) {
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if (isImplicit()) {
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OS << (isDef() ? "imp-def" : "imp-use");
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OS << (isDef() ? "imp-def" : "imp-use");
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NeedComma = true;
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NeedComma = true;
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} else if (isDef()) {
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} else if (isDef()) {
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if (isEarlyClobber())
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OS << "earlyclobber,";
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OS << "def";
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OS << "def";
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NeedComma = true;
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NeedComma = true;
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}
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}
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@ -592,6 +592,13 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
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MI->addOperand(MachineOperand::CreateReg(Reg, true));
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MI->addOperand(MachineOperand::CreateReg(Reg, true));
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}
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}
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break;
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break;
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case 6: // Def of earlyclobber register.
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for (; NumVals; --NumVals, ++i) {
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
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MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
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false, 0, true));
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}
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break;
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case 1: // Use of register.
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case 1: // Use of register.
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case 3: // Immediate.
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case 3: // Immediate.
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case 4: // Addressing mode.
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case 4: // Addressing mode.
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@ -4939,8 +4939,10 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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// Add information to the INLINEASM node to know that this register is
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// Add information to the INLINEASM node to know that this register is
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// set.
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// set.
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OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
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OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
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AsmNodeOperands);
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6 /* EARLYCLOBBER REGDEF */ :
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2 /* REGDEF */ ,
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DAG, AsmNodeOperands);
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break;
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break;
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}
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}
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case InlineAsm::isInput: {
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case InlineAsm::isInput: {
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@ -4959,6 +4961,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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unsigned NumOps =
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unsigned NumOps =
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cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
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cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
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assert(((NumOps & 7) == 2 /*REGDEF*/ ||
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assert(((NumOps & 7) == 2 /*REGDEF*/ ||
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(NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
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(NumOps & 7) == 4 /*MEM*/) &&
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(NumOps & 7) == 4 /*MEM*/) &&
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"Skipped past definitions?");
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"Skipped past definitions?");
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CurOp += (NumOps>>3)+1;
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CurOp += (NumOps>>3)+1;
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@ -4966,7 +4969,8 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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unsigned NumOps =
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unsigned NumOps =
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cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
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cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
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if ((NumOps & 7) == 2 /*REGDEF*/) {
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if ((NumOps & 7) == 2 /*REGDEF*/
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|| (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) {
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// Add NumOps>>3 registers to MatchedRegs.
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// Add NumOps>>3 registers to MatchedRegs.
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RegsForValue MatchedRegs;
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RegsForValue MatchedRegs;
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MatchedRegs.TLI = &TLI;
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MatchedRegs.TLI = &TLI;
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