From 914ce46040f7469c6ca40fb8de9217f8d4813f03 Mon Sep 17 00:00:00 2001
From: Chris Lattner
Date: Thu, 22 Apr 2010 06:28:20 +0000
Subject: [PATCH] another checkpoint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102052 91177308-0d34-0410-b5e6-96231b3b80d8
---
docs/ReleaseNotes.html | 102 ++++++++++++++++++++++++++++-------------
1 file changed, 69 insertions(+), 33 deletions(-)
diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html
index 0a750081e65..fc662618e9d 100644
--- a/docs/ReleaseNotes.html
+++ b/docs/ReleaseNotes.html
@@ -75,6 +75,7 @@ Almost dead code.
+
+
+
+
In addition to changes to the code, between LLVM 2.6 and 2.7, a number of
organization changes have happened:
@@ -387,7 +397,7 @@ organization changes have happened:
Ted Kremenek and Doug Gregor have stepped forward as Code Owners of the
- Clang static analyzer and the Clang Frontend, respectively.
+ Clang static analyzer and the Clang frontend, respectively.
LLVM now has an official Blog at
http://blog.llvm.org. This is a great way
@@ -480,9 +490,16 @@ expose new optimization opportunities:
allows the optimizer to infer the sizes of memory objects in some cases.
This intrinsic is used to implement the GCC __builtin_object_size
extension.
+
LLVM IR now supports marking load and store instructions with "non-temporal" hints (building on the new
+ metadata feature). This hint encourages the code
+ generator to generate non-temporal accesses when possible, which are useful
+ for code that is carefully managing cache behavior. Currently, only the
+ X86 backend provides target support for this feature.
+
LLVM 2.7 has pre-alpha support for unions in LLVM IR.
- Unfortuantely, this support is not really usable in 2.7, so if you're
+ Unfortunately, this support is not really usable in 2.7, so if you're
interested in pushing it forward, please help contribute to LLVM mainline.
@@ -542,8 +559,7 @@ href="http://blog.llvm.org/2009/12/introduction-to-load-elimination-in-gvn.html"
pointer offset expressions to disambiguate pointers. It can catch a few
cases that basicaa cannot, particularly in complex loop nests.
-
As usual, there are countless minor optimization improvements and bug fixes,
- and the default pass ordering has been tweaked for improved optimization
+The default pass ordering has been tweaked for improved optimization
effectiveness.
@@ -563,8 +579,7 @@ href="http://blog.llvm.org/2009/12/introduction-to-load-elimination-in-gvn.html"
the new GDB 7.0 (and later) interfaces for registering debug info for
dynamically generated code.
-
The JIT now defaults
+The JIT now defaults
to compiling eagerly to avoid a race condition in the lazy JIT.
Clients that still want the lazy JIT can switch it on by calling
ExecutionEngine::DisableLazyCompilation(false).
@@ -590,21 +605,48 @@ infrastructure, which allows us to implement more aggressive algorithms and make
it run faster:
-- New instruction selector [blog post?].
-- New LSR with "full strength reduction" mode. Description?
-- Code generator MC'ized except for debug info and EH.
-- New CodeGen Level CSE
-- Combiner-AA improvements, why not on by default?
-- Pre-regalloc tail duplication
-- Codegen level OptimizeExtsPass pass, takes advantage of x86 subregs.
-- Support for the GCC option -fno-schedule-insns
-- Non-temporal load/store, only implemented on X86, see LangRef.html#i_load.
-- MachineSSAUpdater.h
-- X86 and XCore supports returning arbitrary return values, returning too many values is
- supported by returning through a hidden pointer.
-- verbose-asm now produces information about spill slots and loop nests
-- GHC Haskell ABI / calling conv support.
-- Many improvements to debug info
+- The 'llc -asm-verbose' option (which is now the default) has been enhanced
+ to emit many useful comments to .s files indicating information about spill
+ slots and loop nest structure. This should make it much easier to read and
+ understand assembly files. This is wired up in llvm-gcc and clang to
+ the -fverbose-asm option.
+
+- New LSR with "full strength reduction" mode. FIXME: Description?
+
+- A new codegen level Common Subexpression Elimination pass (MachineCSE)
+ is available and enabled by default. It catches redundancies exposed by
+ lowering.
+- A new pre-register-allocation tail duplication pass is available and enabled
+ by default, it can substantially improve branch prediction quality in some
+ cases.
+- A new sign and zero extension optimization pass (OptimizeExtsPass)
+ is available and enabled by default. This pass can takes advantage
+ architecture features like x86-64 implicit zero extension behavior and
+ sub-registers.
+- The code generator now supports a mode where it attempts to preserve the
+ order of instructions in the input code. This is important for source that
+ is hand scheduled and extremely sensitive to scheduling. It is compatible
+ with the GCC -fno-schedule-insns option.
+- The target-independent code generator now supports generating code with
+ arbitrary numbers of result values. Returning more values than was
+ previously supported is handled by returning through a hidden pointer. In
+ 2.7, only the X86 and XCore targets have adopted support for this
+ though.
+- The code generator now supports generating code that follows the
+ Glasgow Haskell Compiler Calling
+ Convention and ABI.
+- The "DAG instruction
+ selection" phase of the code generator has been largely rewritten for
+ 2.7. Previously, tblgen spit out tons of C++ code which was compiled and
+ linked into the target to do the pattern matching, now it emits a much
+ smaller table which is read by the target-independent code. The primary
+ advantages of this approach is that the size and compile time of various
+ targets is much improved. The X86 code generator shrunk by 1.5MB of code,
+ for example.
+- Almost the entire code generator has switched to emitting code through the
+ MC interfaces instead of printing textually to the .s file. This led to a
+ number of cleanups and speedups. In 2.7, debug an exception handling
+ information does not go through MC yet.
@@ -760,7 +802,7 @@ document.
The LLVM interpreter now defaults to not using libffi even
if you have it installed. This makes it more likely that an LLVM built on one
system will work when copied to a similar system. To use libffi,
-configure with --enable-libffi.
+configure with --enable-libffi.
Debug information uses a completely different representation, an LLVM 2.6
.bc file should work with LLVM 2.7, but debug info won't come forward.
@@ -827,7 +869,7 @@ to llvm/System/DataTypes.h.
Intel and AMD machines (IA32, X86-64, AMD64, EMT-64) running Red Hat
Linux, Fedora Core, FreeBSD and AuroraUX (and probably other unix-like
systems).
-PowerPC and X86-based Mac OS X systems, running 10.3 and above in 32-bit
+PowerPC and X86-based Mac OS X systems, running 10.4 and above in 32-bit
and 64-bit modes.
Intel and AMD machines running on Win32 using MinGW libraries (native).
Intel and AMD machines running on Win32 with the Cygwin libraries (limited
@@ -884,7 +926,7 @@ href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVMdev list.
- The MSIL, Alpha, SPU, MIPS, PIC16, Blackfin, MSP430, SystemZ and MicroBlaze
backends are experimental.
-- The llc "-filetype=asm" (the default) is the only
+
- llc "-filetype=asm" (the default) is the only
supported value for this option. The MachO writer is experimental, and
works much better in mainline SVN.
@@ -907,13 +949,10 @@ href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">LLVMdev list.
to generate code for systems that don't have SSE2.
Win64 code generation wasn't widely tested. Everything should work, but we
expect small issues to happen. Also, llvm-gcc cannot build the mingw64
- runtime currently due
- to several
- bugs and due to lack of support for
- the
- 'u' inline assembly constraint and for X87 floating point inline assembly.
+ runtime currently due to lack of support for the 'u' inline assembly
+ constraint and for X87 floating point inline assembly.
The X86-64 backend does not yet support the LLVM IR instruction
- va_arg. Currently, the llvm-gcc and front-ends support variadic
+ va_arg. Currently, front-ends support variadic
argument constructs on X86-64 by lowering them manually.
@@ -1025,9 +1064,6 @@ appropriate nops inserted to ensure restartability.
supported on some targets (these are used when you take the address of a
nested function).
-If you run into GCC extensions which are not supported, please let us know.
-
-