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R600/SI: Make sample intrinsic address parameter type overloaded.
Handle vectors of 1 to 16 integers. Change the intrinsic names to prevent the wrong one from being selected at runtime due to the overloading. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174633 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -519,7 +519,7 @@ class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
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op,
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(outs VReg_128:$vdata),
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(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_128:$vaddr,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
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GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
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asm,
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[]> {
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@ -1186,32 +1186,48 @@ def : Pat <
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VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3)
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>;
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/* int_SI_sample */
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/* int_SI_sample for simple 1D texture lookup */
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def : Pat <
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(int_SI_sample imm:$writemask, VReg_128:$coord, SReg_256:$rsrc, SReg_128:$sampler, imm),
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(IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_128:$coord,
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(int_SI_sample imm:$writemask, (v1i32 VReg_32:$addr),
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SReg_256:$rsrc, SReg_128:$sampler, imm),
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(IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0,
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(i32 (COPY_TO_REGCLASS VReg_32:$addr, VReg_32)),
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SReg_256:$rsrc, SReg_128:$sampler)
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>;
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def : Pat <
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(int_SI_sample imm:$writemask, VReg_128:$coord, SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT),
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(IMAGE_SAMPLE imm:$writemask, 1, 0, 0, 0, 0, 0, 0, VReg_128:$coord,
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SReg_256:$rsrc, SReg_128:$sampler)
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class SamplePattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
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ValueType addr_type> : Pat <
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(name imm:$writemask, (addr_type addr_class:$addr),
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SReg_256:$rsrc, SReg_128:$sampler, imm),
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(opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0,
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(EXTRACT_SUBREG addr_class:$addr, sub0),
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SReg_256:$rsrc, SReg_128:$sampler)
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>;
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/* int_SI_sample_lod */
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def : Pat <
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(int_SI_sample_lod imm:$writemask, VReg_128:$coord, SReg_256:$rsrc, SReg_128:$sampler, imm),
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(IMAGE_SAMPLE_L imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_128:$coord,
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SReg_256:$rsrc, SReg_128:$sampler)
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class SampleRectPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class,
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ValueType addr_type> : Pat <
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(name imm:$writemask, (addr_type addr_class:$addr),
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SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT),
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(opcode imm:$writemask, 1, 0, 0, 0, 0, 0, 0,
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(EXTRACT_SUBREG addr_class:$addr, sub0),
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SReg_256:$rsrc, SReg_128:$sampler)
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>;
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/* int_SI_sample_bias */
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def : Pat <
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(int_SI_sample_bias imm:$writemask, VReg_128:$coord, SReg_256:$rsrc, SReg_128:$sampler, imm),
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(IMAGE_SAMPLE_B imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_128:$coord,
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SReg_256:$rsrc, SReg_128:$sampler)
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>;
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/* int_SI_sample* for texture lookups consuming more address parameters */
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multiclass SamplePatterns<RegisterClass addr_class, ValueType addr_type> {
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def : SamplePattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>;
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def : SampleRectPattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>;
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def : SamplePattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_class, addr_type>;
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def : SamplePattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_class, addr_type>;
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}
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defm : SamplePatterns<VReg_64, v2i32>;
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defm : SamplePatterns<VReg_128, v4i32>;
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defm : SamplePatterns<VReg_256, v8i32>;
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defm : SamplePatterns<VReg_512, v16i32>;
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def CLAMP_SI : CLAMP<VReg_32>;
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def FABS_SI : FABS<VReg_32>;
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@ -22,11 +22,11 @@ let TargetPrefix = "SI", isTarget = 1 in {
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def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v4i32_ty, llvm_i16_ty, llvm_i32_ty], [IntrReadMem]> ;
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def int_SI_wqm : Intrinsic <[], [], []>;
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class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_v4f32_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i32_ty], [IntrReadMem]>;
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class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_anyvector_ty, llvm_v8i32_ty, llvm_v4i32_ty, llvm_i32_ty], [IntrReadMem]>;
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def int_SI_sample : Sample;
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def int_SI_sample_bias : Sample;
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def int_SI_sample_lod : Sample;
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def int_SI_sampleb : Sample;
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def int_SI_samplel : Sample;
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/* Interpolation Intrinsics */
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