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[Hexagon] Deleting unused instructions and adding isCodeGenOnly to some defs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228238 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-02-05 00:10:16 +00:00
parent 69a33e427e
commit 91568ff3aa
3 changed files with 8 additions and 34 deletions
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9
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -4644,7 +4644,7 @@ def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
let Inst{20-16} = Rs;
}
let AddedComplexity = 100, isPredicated = 1 in
let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
"Error; should not emit",
@ -4652,7 +4652,7 @@ def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
(i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
s12ImmPred:$src3)))]>;
let AddedComplexity = 100, isPredicated = 1 in
let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
"Error; should not emit",
@ -4660,7 +4660,7 @@ def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
(i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
(i32 IntRegs:$src3))))]>;
let AddedComplexity = 100, isPredicated = 1 in
let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
"Error; should not emit",
@ -4669,7 +4669,7 @@ def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
s12ImmPred:$src3)))]>;
// Generate frameindex addresses.
let isReMaterializable = 1 in
let isReMaterializable = 1, isCodeGenOnly = 1 in
def TFR_FI : ALU32_ri<(outs IntRegs:$dst), (ins FrameIndex:$src1),
"$dst = add($src1)",
[(set (i32 IntRegs:$dst), ADDRri:$src1)]>;
@ -4780,6 +4780,7 @@ def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
"$dst = CONST64(#$global)",
[(set (i64 DoubleRegs:$dst), imm:$global) ]>;
let isCodeGenOnly = 1 in
def TFR_PdFalse : SInst<(outs PredRegs:$dst), (ins),
"$dst = xor($dst, $dst)",
[(set (i1 PredRegs:$dst), 0)]>;

31
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -1190,14 +1190,6 @@ def : Pat <(truncstorei16 s8ExtPred:$src2, (i32 IntRegs:$src1)),
// memw(Re=#U6)=Rt
// TODO: Needs to be implemented.
// Store predicate:
let hasSideEffects = 0 in
def STriw_pred_V4 : STInst2<(outs),
(ins MEMri:$addr, PredRegs:$src1),
"Error; should not emit",
[]>,
Requires<[HasV4T]>;
let AddedComplexity = 6 in
def : Pat <(store s8ExtPred:$src2, (i32 IntRegs:$src1)),
(S4_storeiri_io IntRegs:$src1, 0, s8ExtPred:$src2)>,
@ -3880,7 +3872,8 @@ def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),
// Transfer global address into a register
let isExtended = 1, opExtendable = 1, AddedComplexity=50, isMoveImm = 1,
isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT in
isAsCheapAsAMove = 1, isReMaterializable = 1, validSubTargets = HasV4SubT,
isCodeGenOnly = 1 in
def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
"$dst = #$src1",
[(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,
@ -3896,16 +3889,6 @@ def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),
(TFRI_V4 tglobaladdr:$src1)>,
Requires<[HasV4T]>;
// Indexed store word - global address.
// memw(Rs+#u6:2)=#S8
let AddedComplexity = 10 in
def STriw_offset_ext_V4 : STInst<(outs),
(ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),
"memw($src1+#$src2) = ##$src3",
[(store (HexagonCONST32 tglobaladdr:$src3),
(add IntRegs:$src1, u6_2ImmPred:$src2))]>,
Requires<[HasV4T]>;
// i8/i16/i32 -> i64 loads
// We need a complexity of 120 here to override preceding handling of
// zextload.
@ -3952,16 +3935,6 @@ def: Storea_pat<SwapSt<atomic_store_16>, I32, addrgp, S2_storerhabs>;
def: Storea_pat<SwapSt<atomic_store_32>, I32, addrgp, S2_storeriabs>;
def: Storea_pat<SwapSt<atomic_store_64>, I64, addrgp, S2_storerdabs>;
// Indexed store double word - global address.
// memw(Rs+#u6:2)=#S8
let AddedComplexity = 10 in
def STrih_offset_ext_V4 : STInst<(outs),
(ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),
"memh($src1+#$src2) = ##$src3",
[(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),
(add IntRegs:$src1, u6_1ImmPred:$src2))]>,
Requires<[HasV4T]>;
//===----------------------------------------------------------------------===//
// :raw for of boundscheck:hi:lo insns
//===----------------------------------------------------------------------===//

2
lib/Target/Hexagon/HexagonInstrInfoV5.td
View File

@ -109,7 +109,7 @@ def TFRI_f : ALU32_ri<(outs IntRegs:$dst), (ins f32Ext:$src1),
Requires<[HasV5T]>;
let isExtended = 1, opExtendable = 2, isPredicated = 1,
hasSideEffects = 0, validSubTargets = HasV5SubT in
hasSideEffects = 0, validSubTargets = HasV5SubT, isCodeGenOnly = 1 in
def TFRI_cPt_f : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, f32Ext:$src2),
"if ($src1) $dst = #$src2",