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Add support for the rep movs[bwd] instructions, and emit them when code

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generating the llvm.memcpy intrinsic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11351 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2004-02-12 17:53:22 +00:00
parent 33aec9efa9
commit 915e5e56d7
5 changed files with 138 additions and 15 deletions
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lib/Target/X86/X86CodeEmitter.cpp
+4
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@@ -470,6 +470,9 @@ void Emitter::emitInstruction(MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
const TargetInstrDescriptor &Desc = II->get(Opcode);
// Emit the repeat opcode prefix as needed.
if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
// Emit instruction prefixes if necessary
if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
@@ -477,6 +480,7 @@ void Emitter::emitInstruction(MachineInstr &MI) {
case X86II::TB:
MCE.emitByte(0x0F); // Two-byte opcode prefix
break;
case X86II::REP: break; // already handled.
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
MCE.emitByte(0xD8+