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when legalizing extremely wide shifts, make sure that

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the shift amounts are in a suitably wide type so that
we don't generate out of range constant shift amounts.

This fixes PR9028.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125458 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2011-02-13 09:10:56 +00:00
parent d302773885
commit 915eeb4887
3 changed files with 21 additions and 3 deletions
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8
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1167,13 +1167,19 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
unsigned NVTBits = NVT.getSizeInBits(); unsigned NVTBits = NVT.getSizeInBits();
EVT ShTy = N->getOperand(1).getValueType(); EVT ShTy = N->getOperand(1).getValueType();
// If this is a large integer being legalized (e.g. an i512) then plop the
// shift amount down as a fixed i32. The target shift amount may be something
// like i8, but this isn't enough to represent the shift amount.
if (NVTBits > 256)
ShTy = MVT::i32;
if (N->getOpcode() == ISD::SHL) { if (N->getOpcode() == ISD::SHL) {
if (Amt > VTBits) { if (Amt > VTBits) {
Lo = Hi = DAG.getConstant(0, NVT); Lo = Hi = DAG.getConstant(0, NVT);
} else if (Amt > NVTBits) { } else if (Amt > NVTBits) {
Lo = DAG.getConstant(0, NVT); Lo = DAG.getConstant(0, NVT);
Hi = DAG.getNode(ISD::SHL, dl, Hi = DAG.getNode(ISD::SHL, dl,
NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
} else if (Amt == NVTBits) { } else if (Amt == NVTBits) {
Lo = DAG.getConstant(0, NVT); Lo = DAG.getConstant(0, NVT);
Hi = InL; Hi = InL;

4
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -2426,11 +2426,11 @@ void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
SDValue Op2 = getValue(I.getOperand(1)); SDValue Op2 = getValue(I.getOperand(1));
MVT ShiftTy = TLI.getShiftAmountTy(); MVT ShiftTy = TLI.getShiftAmountTy();
unsigned ShiftSize = ShiftTy.getSizeInBits();
unsigned Op2Size = Op2.getValueType().getSizeInBits();
// Coerce the shift amount to the right type if we can. // Coerce the shift amount to the right type if we can.
if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
unsigned ShiftSize = ShiftTy.getSizeInBits();
unsigned Op2Size = Op2.getValueType().getSizeInBits();
DebugLoc DL = getCurDebugLoc(); DebugLoc DL = getCurDebugLoc();
// If the operand is smaller than the shift count type, promote it. // If the operand is smaller than the shift count type, promote it.

12
test/CodeGen/X86/crash.ll
View File

@ -187,3 +187,15 @@ for.inc44: ; preds = %for.body
%add46 = add i32 %l_74.0, 1 %add46 = add i32 %l_74.0, 1
br label %for.body br label %for.body
} }
; PR9028
define void @f(i64 %A) nounwind {
entry:
%0 = zext i64 %A to i160
%1 = shl i160 %0, 64
%2 = zext i160 %1 to i576
%3 = zext i96 undef to i576
%4 = or i576 %3, %2
store i576 %4, i576* undef, align 8
ret void
}