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when legalizing extremely wide shifts, make sure that
the shift amounts are in a suitably wide type so that we don't generate out of range constant shift amounts. This fixes PR9028. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125458 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1167,13 +1167,19 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
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unsigned NVTBits = NVT.getSizeInBits();
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EVT ShTy = N->getOperand(1).getValueType();
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// If this is a large integer being legalized (e.g. an i512) then plop the
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// shift amount down as a fixed i32. The target shift amount may be something
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// like i8, but this isn't enough to represent the shift amount.
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if (NVTBits > 256)
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ShTy = MVT::i32;
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if (N->getOpcode() == ISD::SHL) {
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if (Amt > VTBits) {
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Lo = Hi = DAG.getConstant(0, NVT);
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} else if (Amt > NVTBits) {
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Lo = DAG.getConstant(0, NVT);
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Hi = DAG.getNode(ISD::SHL, dl,
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NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
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NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
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} else if (Amt == NVTBits) {
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Lo = DAG.getConstant(0, NVT);
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Hi = InL;
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@ -2426,11 +2426,11 @@ void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
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SDValue Op2 = getValue(I.getOperand(1));
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MVT ShiftTy = TLI.getShiftAmountTy();
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unsigned ShiftSize = ShiftTy.getSizeInBits();
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unsigned Op2Size = Op2.getValueType().getSizeInBits();
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// Coerce the shift amount to the right type if we can.
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if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
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unsigned ShiftSize = ShiftTy.getSizeInBits();
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unsigned Op2Size = Op2.getValueType().getSizeInBits();
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DebugLoc DL = getCurDebugLoc();
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// If the operand is smaller than the shift count type, promote it.
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@ -187,3 +187,15 @@ for.inc44: ; preds = %for.body
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%add46 = add i32 %l_74.0, 1
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br label %for.body
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}
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; PR9028
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define void @f(i64 %A) nounwind {
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entry:
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%0 = zext i64 %A to i160
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%1 = shl i160 %0, 64
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%2 = zext i160 %1 to i576
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%3 = zext i96 undef to i576
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%4 = or i576 %3, %2
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store i576 %4, i576* undef, align 8
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ret void
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}
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