From 91625aab6057c46cb167f7ac4a487fe02993acb1 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 14 Jun 2012 01:17:59 +0000 Subject: [PATCH] Add AT to the list of registers clobbered by branches so that it is available as a scratch register when they are expanded to long branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158432 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsInstrInfo.td | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index a9af4e65dfa..b6cfe6d53e0 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -561,6 +561,7 @@ class CBranch op, string instr_asm, PatFrag cond_op, RegisterClass RC>: let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; + let Defs = [AT]; } class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, @@ -572,6 +573,7 @@ class CBranchZero op, bits<5> _rt, string instr_asm, PatFrag cond_op, let isBranch = 1; let isTerminator = 1; let hasDelaySlot = 1; + let Defs = [AT]; } // SetCC @@ -601,6 +603,7 @@ class JumpFJ op, string instr_asm>: let hasDelaySlot = 1; let Predicates = [RelocStatic, HasStandardEncoding]; let DecoderMethod = "DecodeJumpTarget"; + let Defs = [AT]; } // Unconditional branch @@ -614,6 +617,7 @@ class UncondBranch op, string instr_asm>: let isBarrier = 1; let hasDelaySlot = 1; let Predicates = [RelocPIC, HasStandardEncoding]; + let Defs = [AT]; } let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,