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[Hexagon] Renaming A2_addi and formatting.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228318 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-02-05 17:49:13 +00:00
parent bf9263158f
commit 916b91acf1
7 changed files with 34 additions and 37 deletions
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8
lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
View File

@ -90,7 +90,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
"Not a predicate register");
if (!TII->isValidOffset(Hexagon::S2_storeri_io, Offset)) {
if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
if (!TII->isValidOffset(Hexagon::A2_addi, Offset)) {
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::CONST32_Int_Real),
HEXAGON_RESERVED_REG_1).addImm(Offset);
@ -104,7 +104,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
.addReg(HEXAGON_RESERVED_REG_1)
.addImm(0).addReg(HEXAGON_RESERVED_REG_2);
} else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_addi),
HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrpr),
HEXAGON_RESERVED_REG_2).addReg(SrcReg);
@ -134,7 +134,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
assert(MI->getOperand(2).isImm() && "Not an offset");
int Offset = MI->getOperand(2).getImm();
if (!TII->isValidOffset(Hexagon::L2_loadri_io, Offset)) {
if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
if (!TII->isValidOffset(Hexagon::A2_addi, Offset)) {
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::CONST32_Int_Real),
HEXAGON_RESERVED_REG_1).addImm(Offset);
@ -149,7 +149,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),
DstReg).addReg(HEXAGON_RESERVED_REG_2);
} else {
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_addi),
HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),
HEXAGON_RESERVED_REG_2)

8
lib/Target/Hexagon/HexagonHardwareLoops.cpp
View File

@ -349,7 +349,7 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L,
unsigned PhiOpReg = Phi->getOperand(i).getReg();
MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
unsigned UpdOpc = DI->getOpcode();
bool isAdd = (UpdOpc == Hexagon::ADD_ri);
bool isAdd = (UpdOpc == Hexagon::A2_addi);
if (isAdd) {
// If the register operand to the add is the PHI we're
@ -775,7 +775,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
} else {
const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::A2_sub) :
(RegToImm ? TII->get(Hexagon::SUB_ri) :
TII->get(Hexagon::ADD_ri));
TII->get(Hexagon::A2_addi));
unsigned SubR = MRI->createVirtualRegister(IntRC);
MachineInstrBuilder SubIB =
BuildMI(*PH, InsertPos, DL, SubD, SubR);
@ -803,7 +803,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
} else {
// Generate CountR = ADD DistR, AdjVal
unsigned AddR = MRI->createVirtualRegister(IntRC);
const MCInstrDesc &AddD = TII->get(Hexagon::ADD_ri);
MCInstrDesc const &AddD = TII->get(Hexagon::A2_addi);
BuildMI(*PH, InsertPos, DL, AddD, AddR)
.addReg(DistR, 0, DistSR)
.addImm(AdjV);
@ -1269,7 +1269,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
unsigned PhiReg = Phi->getOperand(i).getReg();
MachineInstr *DI = MRI->getVRegDef(PhiReg);
unsigned UpdOpc = DI->getOpcode();
bool isAdd = (UpdOpc == Hexagon::ADD_ri);
bool isAdd = (UpdOpc == Hexagon::A2_addi);
if (isAdd) {
// If the register operand to the add/sub is the PHI we are looking

8
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -447,7 +447,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
Chain);
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl,
MVT::i64, SDValue(Result_1, 0));
SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl,
SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl,
MVT::i32, Base, TargetConstVal,
SDValue(Result_1, 1));
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
@ -525,7 +525,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
SDValue(Result_2,0),
SDValue(Result_1,0));
// Add offset to base.
SDNode* Result_4 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
SDNode* Result_4 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
Base, TargetConstVal,
SDValue(Result_1, 1));
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
@ -621,7 +621,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
LD->getValueType(0),
MVT::Other, Base, TargetConst0,
Chain);
SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
Base, TargetConstVal,
SDValue(Result_1, 1));
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
@ -713,7 +713,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
// Build splitted incriment instruction.
SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
Base,
TargetConstVal,
SDValue(Result_1, 0));

8
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -696,7 +696,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
return (isUInt<6>(MI->getOperand(1).getImm()) &&
isInt<6>(MI->getOperand(2).getImm()));
case Hexagon::ADD_ri:
case Hexagon::A2_addi:
return isInt<8>(MI->getOperand(2).getImm());
case Hexagon::A2_aslh:
@ -1107,7 +1107,7 @@ isValidOffset(const int Opcode, const int Offset) const {
return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
(Offset <= Hexagon_MEMB_OFFSET_MAX);
case Hexagon::ADD_ri:
case Hexagon::A2_addi:
case Hexagon::TFR_FI:
return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
(Offset <= Hexagon_ADDI_OFFSET_MAX);
@ -1308,8 +1308,8 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::A4_pzxthfnew:
case Hexagon::A4_pzxtht:
case Hexagon::A4_pzxthtnew:
case Hexagon::ADD_ri_cPt:
case Hexagon::ADD_ri_cNotPt:
case Hexagon::A2_paddit:
case Hexagon::A2_paddif:
case Hexagon::C2_ccombinewt:
case Hexagon::C2_ccombinewf:
return true;

25
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -60,8 +60,6 @@ def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
return XformUToUM1Imm(imm);
}]>;
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Compare
//===----------------------------------------------------------------------===//
@ -366,12 +364,10 @@ class T_Addri_Pred <bit PredNot, bit PredNew>
// A2_addi: Add a signed immediate to a register.
//===----------------------------------------------------------------------===//
let hasNewValue = 1, hasSideEffects = 0 in
class T_Addri <Operand immOp, list<dag> pattern = [] >
class T_Addri <Operand immOp>
: ALU32_ri <(outs IntRegs:$Rd),
(ins IntRegs:$Rs, immOp:$s16),
"$Rd = add($Rs, #$s16)", pattern,
//[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), (s16ExtPred:$s16)))],
"", ALU32_ADDI_tc_1_SLOT0123> {
"$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> {
bits<5> Rd;
bits<5> Rs;
bits<16> s16;
@ -389,9 +385,9 @@ class T_Addri <Operand immOp, list<dag> pattern = [] >
//===----------------------------------------------------------------------===//
multiclass Addri_Pred<string mnemonic, bit PredNot> {
let isPredicatedFalse = PredNot in {
def _c#NAME : T_Addri_Pred<PredNot, 0>;
def NAME : T_Addri_Pred<PredNot, 0>;
// Predicate new
def _cdn#NAME : T_Addri_Pred<PredNot, 1>;
def NAME#new : T_Addri_Pred<PredNot, 1>;
}
}
@ -400,19 +396,20 @@ multiclass Addri_base<string mnemonic, SDNode OpNode> {
let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
isPredicable = 1 in
def NAME : T_Addri< s16Ext, // Rd=add(Rs,#s16)
[(set (i32 IntRegs:$Rd),
(add IntRegs:$Rs, s16ExtPred:$s16))]>;
def A2_#NAME : T_Addri<s16Ext>;
let opExtendable = 3, isExtentSigned = 1, opExtentBits = 8,
hasSideEffects = 0, isPredicated = 1 in {
defm Pt : Addri_Pred<mnemonic, 0>;
defm NotPt : Addri_Pred<mnemonic, 1>;
defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>;
defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>;
}
}
}
defm ADD_ri : Addri_base<"add", add>, ImmRegRel, PredNewRel;
defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel;
def: Pat<(i32 (add I32:$Rs, s16ExtPred:$s16)),
(i32 (A2_addi I32:$Rs, imm:$s16))>;
//===----------------------------------------------------------------------===//
// Template class used for the following ALU32 instructions.

2
lib/Target/Hexagon/HexagonIntrinsics.td
View File

@ -649,7 +649,7 @@ def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>;
* ALU32/ALU *
*********************************************************************/
def : T_RR_pat<A2_add, int_hexagon_A2_add>;
def : T_RI_pat<ADD_ri, int_hexagon_A2_addi>;
def : T_RI_pat<A2_addi, int_hexagon_A2_addi>;
def : T_RR_pat<A2_sub, int_hexagon_A2_sub>;
def : T_IR_pat<SUB_ri, int_hexagon_A2_subri>;
def : T_RR_pat<A2_and, int_hexagon_A2_and>;

12
lib/Target/Hexagon/HexagonRegisterInfo.cpp
View File

@ -170,7 +170,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.getOperand(0).getReg();
// Check if offset can fit in addi.
if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) {
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
@ -178,7 +178,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
dstReg).addReg(FrameReg).addReg(dstReg);
} else {
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
TII.get(Hexagon::ADD_ri),
TII.get(Hexagon::A2_addi),
dstReg).addReg(FrameReg).addImm(Offset);
}
@ -196,7 +196,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
unsigned resReg = HEXAGON_RESERVED_REG_1;
// Check if offset can fit in addi.
if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) {
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
@ -204,7 +204,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
resReg).addReg(FrameReg).addReg(resReg);
} else {
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
TII.get(Hexagon::ADD_ri),
TII.get(Hexagon::A2_addi),
resReg).addReg(FrameReg).addImm(Offset);
}
MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true);
@ -228,7 +228,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(),
false, false, false);
MI.getOperand(FIOperandNum+1).ChangeToImmediate(FrameSize+Offset);
} else if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
} else if (!TII.isValidOffset(Hexagon::A2_addi, Offset)) {
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
TII.get(Hexagon::CONST32_Int_Real), ResReg).addImm(Offset);
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
@ -239,7 +239,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
} else {
BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
TII.get(Hexagon::ADD_ri), ResReg).addReg(FrameReg).
TII.get(Hexagon::A2_addi), ResReg).addReg(FrameReg).
addImm(Offset);
MI.getOperand(FIOperandNum).ChangeToRegister(ResReg, false, false,
true);