Implement necessary bits for flt_rounds gcc builtin.

Codegen bits and llvm-gcc support will follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44182 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/SelectionDAGNodes.h

@@ -390,6 +390,14 @@ namespace ISD {
     // precision down to the specified precision (currently always 64->32).
     FP_ROUND,
 
+    // FLT_ROUNDS - Returns current rounding mode:
+    // -1 Undefined
+    //  0 Round to 0
+    //  1 Round to nearest
+    //  2 Round to +inf
+    //  3 Round to -inf
+    FLT_ROUNDS,
+
     // FP_ROUND_INREG - This operator takes a floating point register, and
     // rounds it to a floating point value.  It then promotes it and returns it
     // in a register of the same size.  This operation effectively just discards

include/llvm/Intrinsics.td

@@ -262,6 +262,11 @@ def int_init_trampoline : Intrinsic<[llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty,
                                      llvm_ptr_ty], []>,
                           GCCBuiltin<"__builtin_init_trampoline">;
 
+//===-------------------------- Other Intrinsics --------------------------===//
+//
+def int_flt_rounds : Intrinsic<[llvm_i32_ty]>,
+                     GCCBuiltin<"__builtin_flt_rounds">;
+
 //===----------------------------------------------------------------------===//
 // Target-specific intrinsics
 //===----------------------------------------------------------------------===//

lib/CodeGen/IntrinsicLowering.cpp

@@ -856,6 +856,11 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
     }
     break;
   }
+  case Intrinsic::flt_rounds:
+     // Lower to "round to the nearest"
+     if (CI->getType() != Type::VoidTy)
+       CI->replaceAllUsesWith(ConstantInt::get(CI->getType(), 1));
+     break;
   }
 
   assert(CI->use_empty() &&

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

@@ -3676,6 +3676,20 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     AddLegalizedOperand(SDOperand(Node, 0), Result);
     AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
     return Op.ResNo ? Tmp1 : Result;
+  }
+   case ISD::FLT_ROUNDS: {
+    MVT::ValueType VT = Node->getValueType(0);
+    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
+    default: assert(0 && "This action not supported for this op yet!");
+    case TargetLowering::Custom:
+      Result = TLI.LowerOperation(Op, DAG);
+      if (Result.Val) break;
+      // Fall Thru
+    case TargetLowering::Legal:
+      // If this operation is not supported, lower it to constant 1
+      Result = DAG.getConstant(1, VT);
+      break;
+    }
   }
   }
   

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -3739,6 +3739,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
   case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
   case ISD::TRUNCATE:    return "truncate";
   case ISD::FP_ROUND:    return "fp_round";
+  case ISD::FLT_ROUNDS:  return "flt_rounds";
   case ISD::FP_ROUND_INREG: return "fp_round_inreg";
   case ISD::FP_EXTEND:   return "fp_extend";
 

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -2930,6 +2930,10 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
     DAG.setRoot(Tmp.getValue(1));
     return 0;
   }
+  case Intrinsic::flt_rounds: {
+    setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32));
+    return 0;
+  }
   }
 }