6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2026-04-26 12:20:42 +00:00
Code Issues Projects Releases Wiki Activity

Consider the case where xor by -1 and xor by 128 have been combined already to

Browse Source 
produce an xor by 127.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54906 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nick Lewycky
2008-08-17 19:58:24 +00:00
parent b20d685c6f
commit 91a0f78265
2 changed files with 42 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/Transforms/Scalar/InstructionCombining.cpp
+23 -1
View File
@@ -5503,8 +5503,8 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {
return new ICmpInst(I.getPredicate(), Op0I->getOperand(0),
Op1I->getOperand(0));
} else {
// icmp u/s (a ^ signbit), (b ^ signbit) --> icmp s/u a, b
if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0I->getOperand(1))) {
// icmp u/s (a ^ signbit), (b ^ signbit) --> icmp s/u a, b
if (CI->getValue().isSignBit()) {
ICmpInst::Predicate Pred = I.isSignedPredicate()
? I.getUnsignedPredicate()
@@ -5512,6 +5512,17 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {
return new ICmpInst(Pred, Op0I->getOperand(0),
Op1I->getOperand(0));
}
// icmp u/s (a ^ ~signbit), (b ^ ~signbit) --> icmp s/u b, a
if ((~CI->getValue()).isSignBit()) {
ICmpInst::Predicate Pred = I.isSignedPredicate()
? I.getUnsignedPredicate()
: I.getSignedPredicate();
Pred = I.getSwappedPredicate(Pred);
return new ICmpInst(Pred, Op0I->getOperand(0),
Op1I->getOperand(0));
}
}
}
break;
@@ -5818,6 +5829,17 @@ Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI,
return new ICmpInst(Pred, LHSI->getOperand(0),
ConstantInt::get(RHSV ^ SignBit));
}
// (icmp u/s (xor A ~SignBit), C) -> (icmp ~s/u A, (xor C ~SignBit))
if (!ICI.isEquality() && (~XorCST->getValue()).isSignBit()) {
const APInt &NotSignBit = XorCST->getValue();
ICmpInst::Predicate Pred = ICI.isSignedPredicate()
? ICI.getUnsignedPredicate()
: ICI.getSignedPredicate();
Pred = ICI.getSwappedPredicate(Pred);
return new ICmpInst(Pred, LHSI->getOperand(0),
ConstantInt::get(RHSV ^ NotSignBit));
}
}
break;
case Instruction::And: // (icmp pred (and X, AndCST), RHS)