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Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere. Propagate this bit and the earlyclobber bit through SDISel. Change linear-scan RA not to allocate regs in a way that conflicts with an earlyclobber. See also comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -28,6 +28,7 @@
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/Allocator.h"
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#include <cmath>
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#include <map>
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namespace llvm {
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@ -64,6 +65,22 @@ namespace llvm {
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AliasAnalysis *aa_;
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LiveVariables* lv_;
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/// AsmsWithEarlyClobber - maps a virtual register number to all the
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/// inline asm's that have the register marked earlyclobber.
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///
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std::multimap<unsigned, MachineInstr*> AsmsThatEarlyClobber;
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/// AsmsWithEarlyClobberConflict - maps a virtual register number
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/// to all the inline asm's that have earlyclobber operands elsewhere
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/// and use the register as a (non-earlyclobber) input.
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///
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/// Note: earlyclobber operands may not be assigned the same register as
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/// each other, or as earlyclobber-conflict operands. However two
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/// earlyclobber-conflict operands may be assigned the same register if
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/// they happen to contain the same value.
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///
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std::multimap<unsigned, MachineInstr*> AsmsWithEarlyClobberConflict;
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/// Special pool allocator for VNInfo's (LiveInterval val#).
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///
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BumpPtrAllocator VNInfoAllocator;
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@ -336,6 +353,11 @@ namespace llvm {
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unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
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unsigned PhysReg) const;
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/// noEarlyclobberConflict - see whether virtual reg VReg has a conflict
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/// with hard reg HReg because HReg is used as an earlyclobber register in
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/// asm that also has VReg live into or across it.
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bool noEarlyclobberConflict(unsigned VReg, VirtRegMap &vrm, unsigned HReg);
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/// computeNumbering - Compute the index numbering.
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void computeNumbering();
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@ -73,6 +73,12 @@ private:
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/// for description of earlyclobber.
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bool IsEarlyClobber : 1;
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/// OverlapsEarlyClobber - True if this MO_Register operand is used as an
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/// input to an inline asm that has the earlyclobber bit set on some other
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/// operand. Flag is not valid for any other case. See gcc doc
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/// for description of earlyclobber.
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bool OverlapsEarlyClobber : 1;
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/// SubReg - Subregister number, only valid for MO_Register. A value of 0
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/// indicates the MO_Register has no subReg.
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unsigned char SubReg;
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@ -182,6 +188,11 @@ public:
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return IsEarlyClobber;
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}
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bool overlapsEarlyClobber() const {
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assert(isRegister() && "Wrong MachineOperand accessor");
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return OverlapsEarlyClobber;
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}
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/// getNextOperandForReg - Return the next MachineOperand in the function that
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/// uses or defines this register.
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MachineOperand *getNextOperandForReg() const {
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@ -232,6 +243,11 @@ public:
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IsEarlyClobber = Val;
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}
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void setOverlapsEarlyClobber(bool Val = true) {
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assert(isRegister() && "Wrong MachineOperand accessor");
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OverlapsEarlyClobber = Val;
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}
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//===--------------------------------------------------------------------===//
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// Accessors for various operand types.
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//===--------------------------------------------------------------------===//
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@ -337,13 +353,15 @@ public:
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static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
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bool isKill = false, bool isDead = false,
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unsigned SubReg = 0,
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bool isEarlyClobber = false) {
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bool isEarlyClobber = false,
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bool overlapsEarlyClobber = false) {
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MachineOperand Op(MachineOperand::MO_Register);
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Op.IsDef = isDef;
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Op.IsImp = isImp;
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Op.IsKill = isKill;
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Op.IsDead = isDead;
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Op.IsEarlyClobber = isEarlyClobber;
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Op.OverlapsEarlyClobber = overlapsEarlyClobber;
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Op.Contents.Reg.RegNo = Reg;
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Op.Contents.Reg.Prev = 0;
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Op.Contents.Reg.Next = 0;
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@ -390,6 +408,7 @@ public:
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IsKill = MO.IsKill;
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IsDead = MO.IsDead;
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IsEarlyClobber = MO.IsEarlyClobber;
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OverlapsEarlyClobber = MO.OverlapsEarlyClobber;
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SubReg = MO.SubReg;
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ParentMI = MO.ParentMI;
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Contents = MO.Contents;
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@ -361,7 +361,8 @@ namespace llvm {
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void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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DenseMap<SDValue, unsigned> &VRBaseMap,
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bool overlapsEarlyClobber = false);
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void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO);
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@ -1325,7 +1325,8 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
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false, false, false);
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else {
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AsmPrinter *AP = const_cast<AsmPrinter*>(this);
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if ((OpFlags & 7) == 4 /*ADDR MODE*/) {
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if ((OpFlags & 7) == 4 /*ADDR MODE*/ ||
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(OpFlags & 7) == 7) /*ADDR MODE OVERLAPS EARLYCLOBBER*/ {
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Error = AP->PrintAsmMemoryOperand(MI, OpNo, AsmPrinterVariant,
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Modifier[0] ? Modifier : 0);
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} else {
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@ -673,7 +673,10 @@ exit:
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/// registers. for some ordering of the machine instructions [1,N] a
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/// live interval is an interval [i, j) where 1 <= i <= j < N for
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/// which a variable is live
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void LiveIntervals::computeIntervals() {
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void LiveIntervals::computeIntervals() {
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AsmsThatEarlyClobber.clear();
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AsmsWithEarlyClobberConflict.clear();
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DOUT << "********** COMPUTING LIVE INTERVALS **********\n"
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<< "********** Function: "
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<< ((Value*)mf_->getFunction())->getName() << '\n';
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@ -710,8 +713,17 @@ void LiveIntervals::computeIntervals() {
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for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
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MachineOperand &MO = MI->getOperand(i);
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// handle register defs - build intervals
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if (MO.isRegister() && MO.getReg() && MO.isDef())
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if (MO.isRegister() && MO.getReg() && MO.isDef()) {
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handleRegisterDef(MBB, MI, MIIndex, MO, i);
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if (MO.isEarlyClobber()) {
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AsmsThatEarlyClobber.insert(std::make_pair(MO.getReg(), MI));
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}
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}
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if (MO.isRegister() && !MO.isDef() &&
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MO.getReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()) &&
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MO.overlapsEarlyClobber()) {
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AsmsWithEarlyClobberConflict.insert(std::make_pair(MO.getReg(), MI));
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}
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}
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MIIndex += InstrSlots::NUM;
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@ -740,6 +752,72 @@ bool LiveIntervals::findLiveInMBBs(const LiveRange &LR,
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return ResVal;
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}
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/// noEarlyclobberConflict - see whether virtual reg VReg has a conflict with
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/// hard reg HReg because of earlyclobbers.
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///
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/// Earlyclobber operands may not be assigned the same register as
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/// each other, or as earlyclobber-conflict operands (i.e. those that
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/// are non-earlyclobbered inputs to an asm that also has earlyclobbers).
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///
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/// Thus there are two cases to check for:
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/// 1. VReg is an earlyclobber-conflict register and HReg is an earlyclobber
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/// register in some asm that also has VReg as an input.
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/// 2. VReg is an earlyclobber register and HReg is an earlyclobber-conflict
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/// input elsewhere in some asm.
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/// In both cases HReg can be assigned by the user, or assigned early in
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/// register allocation.
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///
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/// Dropping the distinction between earlyclobber and earlyclobber-conflict,
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/// keeping only one multimap, looks promising, but two earlyclobber-conflict
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/// operands may be assigned the same register if they happen to contain the
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/// same value, and that implementation would prevent this.
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///
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bool LiveIntervals::noEarlyclobberConflict(unsigned VReg, VirtRegMap &vrm,
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unsigned HReg) {
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typedef std::multimap<unsigned, MachineInstr*>::iterator It;
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// Short circuit the most common case.
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if (AsmsWithEarlyClobberConflict.size()!=0) {
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std::pair<It, It> x = AsmsWithEarlyClobberConflict.equal_range(VReg);
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for (It I = x.first; I!=x.second; I++) {
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MachineInstr* MI = I->second;
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for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isEarlyClobber()) {
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unsigned PhysReg = MO.getReg();
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if (PhysReg && TargetRegisterInfo::isVirtualRegister(PhysReg)) {
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if (!vrm.hasPhys(PhysReg))
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continue;
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PhysReg = vrm.getPhys(PhysReg);
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}
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if (PhysReg==HReg)
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return false;
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}
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}
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}
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}
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// Short circuit the most common case.
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if (AsmsThatEarlyClobber.size()!=0) {
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std::pair<It, It> x = AsmsThatEarlyClobber.equal_range(VReg);
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for (It I = x.first; I!=x.second; I++) {
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MachineInstr* MI = I->second;
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for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.overlapsEarlyClobber()) {
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unsigned PhysReg = MO.getReg();
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if (PhysReg && TargetRegisterInfo::isVirtualRegister(PhysReg)) {
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if (!vrm.hasPhys(PhysReg))
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continue;
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PhysReg = vrm.getPhys(PhysReg);
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}
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if (PhysReg==HReg)
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return false;
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}
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}
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}
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}
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return true;
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}
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LiveInterval* LiveIntervals::createInterval(unsigned reg) {
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float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
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@ -109,6 +109,7 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
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// register's use/def lists.
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if (isRegister()) {
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assert(!isEarlyClobber());
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assert(!isEarlyClobber() && !overlapsEarlyClobber());
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setReg(Reg);
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} else {
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// Otherwise, change this to a register and set the reg#.
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@ -128,6 +129,7 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
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IsKill = isKill;
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IsDead = isDead;
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IsEarlyClobber = false;
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OverlapsEarlyClobber = false;
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SubReg = 0;
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}
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@ -183,13 +185,20 @@ void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
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OS << "%mreg" << getReg();
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}
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if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
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if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber() ||
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overlapsEarlyClobber()) {
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OS << "<";
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bool NeedComma = false;
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if (overlapsEarlyClobber()) {
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NeedComma = true;
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OS << "overlapsearly";
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}
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if (isImplicit()) {
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if (NeedComma) OS << ",";
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OS << (isDef() ? "imp-def" : "imp-use");
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NeedComma = true;
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} else if (isDef()) {
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if (NeedComma) OS << ",";
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if (isEarlyClobber())
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OS << "earlyclobber,";
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OS << "def";
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@ -1050,7 +1050,8 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
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TargetRegisterClass::iterator E = RC->allocation_order_end(*mf_);
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assert(I != E && "No allocatable register in this register class!");
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for (; I != E; ++I)
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if (prt_->isRegAvail(*I)) {
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if (prt_->isRegAvail(*I) &&
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li_->noEarlyclobberConflict(cur->reg, *vrm_, *I)) {
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FreeReg = *I;
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if (FreeReg < inactiveCounts.size())
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FreeRegInactiveCount = inactiveCounts[FreeReg];
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@ -1070,7 +1071,8 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
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for (; I != E; ++I) {
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unsigned Reg = *I;
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if (prt_->isRegAvail(Reg) && Reg < inactiveCounts.size() &&
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FreeRegInactiveCount < inactiveCounts[Reg]) {
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FreeRegInactiveCount < inactiveCounts[Reg] &&
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li_->noEarlyclobberConflict(cur->reg, *vrm_, Reg)) {
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FreeReg = Reg;
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FreeRegInactiveCount = inactiveCounts[Reg];
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if (FreeRegInactiveCount == MaxInactiveCount)
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@ -231,7 +231,8 @@ unsigned ScheduleDAG::getVR(SDValue Op,
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void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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DenseMap<SDValue, unsigned> &VRBaseMap,
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bool overlapsEarlyClobber) {
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if (Op.isMachineOpcode()) {
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// Note that this case is redundant with the final else block, but we
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// include it because it is the most common and it makes the logic
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@ -244,7 +245,9 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
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const TargetInstrDesc &TID = MI->getDesc();
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bool isOptDef = IIOpNum < TID.getNumOperands() &&
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TID.OpInfo[IIOpNum].isOptionalDef();
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MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
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MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, false, false,
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false, 0, false,
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overlapsEarlyClobber));
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// Verify that it is right.
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assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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@ -278,7 +281,9 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
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const ConstantFP *CFP = F->getConstantFPValue();
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MI->addOperand(MachineOperand::CreateFPImm(CFP));
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} else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
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MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, false,
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false, false, 0, false,
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overlapsEarlyClobber));
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} else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
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} else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
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@ -314,7 +319,9 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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unsigned VReg = getVR(Op, VRBaseMap);
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MI->addOperand(MachineOperand::CreateReg(VReg, false));
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MI->addOperand(MachineOperand::CreateReg(VReg, false, false,
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false, false, 0, false,
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overlapsEarlyClobber));
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// Verify that it is right. Note that the reg class of the physreg and the
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// vreg don't necessarily need to match, but the target copy insertion has
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@ -596,6 +603,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
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// Add all of the operand registers to the instruction.
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for (unsigned i = 2; i != NumOps;) {
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bool overlapsEarlyClobber = false;
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unsigned Flags =
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cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
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unsigned NumVals = Flags >> 3;
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@ -618,13 +626,18 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
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false, 0, true));
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}
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break;
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case 7: // Addressing mode overlapping earlyclobber.
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case 5: // Use of register overlapping earlyclobber.
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overlapsEarlyClobber = true;
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// fall through
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case 1: // Use of register.
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case 3: // Immediate.
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case 4: // Addressing mode.
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// The addressing mode has been selected, just add all of the
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// operands to the machine instruction.
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for (; NumVals; --NumVals, ++i)
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AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
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AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
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overlapsEarlyClobber);
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break;
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}
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}
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@ -4909,8 +4909,10 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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assert(OpInfo.isIndirect && "Memory output must be indirect operand");
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// Add information to the INLINEASM node to know about this output.
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unsigned ResOpType = 4/*MEM*/ | (1 << 3);
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AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
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unsigned ResOpType = SawEarlyClobber ?
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7 /* MEM OVERLAPS EARLYCLOBBER */ :
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4/*MEM*/;
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AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType | (1<<3),
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TLI.getPointerTy()));
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AsmNodeOperands.push_back(OpInfo.CallOperand);
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break;
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@ -4963,7 +4965,8 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
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assert(((NumOps & 7) == 2 /*REGDEF*/ ||
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(NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
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(NumOps & 7) == 4 /*MEM*/) &&
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(NumOps & 7) == 4 /*MEM*/ ||
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(NumOps & 7) == 7 /*MEM OVERLAPS EARLYCLOBBER*/) &&
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"Skipped past definitions?");
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CurOp += (NumOps>>3)+1;
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}
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@ -4985,14 +4988,17 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
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// Use the produced MatchedRegs object to
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MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
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MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
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MatchedRegs.AddInlineAsmOperands(SawEarlyClobber ?
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1 /*REGUSE*/ :
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5 /*REGUSE OVERLAPS EARLYCLOBBER*/,
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DAG, AsmNodeOperands);
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break;
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} else {
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assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
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assert(((NumOps & 7) == 7/*MEM OVERLAPS EARLYCLOBBER */ ||
|
||||
(NumOps & 7) == 4) && "Unknown matching constraint!");
|
||||
assert((NumOps >> 3) == 1 && "Unexpected number of operands");
|
||||
// Add information to the INLINEASM node to know about this input.
|
||||
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
|
||||
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
|
||||
AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps,
|
||||
TLI.getPointerTy()));
|
||||
AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
|
||||
break;
|
||||
@ -5024,8 +5030,10 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
|
||||
"Memory operands expect pointer values");
|
||||
|
||||
// Add information to the INLINEASM node to know about this input.
|
||||
unsigned ResOpType = 4/*MEM*/ | (1 << 3);
|
||||
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
|
||||
unsigned ResOpType = SawEarlyClobber ?
|
||||
7 /* MEM OVERLAPS EARLYCLOBBER */ :
|
||||
4/*MEM*/;
|
||||
AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType | (1<<3),
|
||||
TLI.getPointerTy()));
|
||||
AsmNodeOperands.push_back(InOperandVal);
|
||||
break;
|
||||
@ -5043,16 +5051,18 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
|
||||
|
||||
OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
|
||||
|
||||
OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
|
||||
AsmNodeOperands);
|
||||
OpInfo.AssignedRegs.AddInlineAsmOperands(SawEarlyClobber ?
|
||||
5 /*REGUSE OVERLAPS EARLYCLOBBER*/:
|
||||
1/*REGUSE*/,
|
||||
DAG, AsmNodeOperands);
|
||||
break;
|
||||
}
|
||||
case InlineAsm::isClobber: {
|
||||
// Add the clobbered value to the operand list, so that the register
|
||||
// allocator is aware that the physreg got clobbered.
|
||||
if (!OpInfo.AssignedRegs.Regs.empty())
|
||||
OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
|
||||
AsmNodeOperands);
|
||||
OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
|
||||
DAG, AsmNodeOperands);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
@ -1113,7 +1113,8 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
|
||||
|
||||
while (i != e) {
|
||||
unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
|
||||
if ((Flags & 7) != 4 /*MEM*/) {
|
||||
if ((Flags & 7) != 4 /*MEM*/ &&
|
||||
(Flags & 7) != 7 /*MEM OVERLAPS EARLYCLOBBER*/) {
|
||||
// Just skip over this operand, copying the operands verbatim.
|
||||
Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
|
||||
i += (Flags >> 3) + 1;
|
||||
@ -1128,7 +1129,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
|
||||
|
||||
// Add this to the output node.
|
||||
MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
|
||||
Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
|
||||
Ops.push_back(CurDAG->getTargetConstant((Flags & 7) | (SelOps.size()<< 3),
|
||||
IntPtrTy));
|
||||
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
|
||||
i += 2;
|
||||
|
24
test/CodeGen/X86/2008-09-17-inline-asm-1.ll
Normal file
24
test/CodeGen/X86/2008-09-17-inline-asm-1.ll
Normal file
@ -0,0 +1,24 @@
|
||||
; RUN: llvm-as < %s | llc -o - -march=x86 | not grep "movl %eax, %eax"
|
||||
; RUN: llvm-as < %s | llc -o - -march=x86 | not grep "movl %edx, %edx"
|
||||
; RUN: llvm-as < %s | llc -o - -march=x86 | not grep "movl (%eax), %eax"
|
||||
; RUN: llvm-as < %s | llc -o - -march=x86 | not grep "movl (%edx), %edx"
|
||||
|
||||
; %0 must not be put in EAX or EDX.
|
||||
; In the first asm, $0 and $2 must not be put in EAX.
|
||||
; In the second asm, $0 and $2 must not be put in EDX.
|
||||
; This is kind of hard to test thoroughly, but the things above should continue
|
||||
; to pass, I think.
|
||||
; ModuleID = '<stdin>'
|
||||
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
|
||||
target triple = "i386-apple-darwin8"
|
||||
@x = common global i32 0 ; <i32*> [#uses=1]
|
||||
|
||||
define i32 @aci(i32* %pw) nounwind {
|
||||
entry:
|
||||
%0 = load i32* @x, align 4 ; <i32> [#uses=1]
|
||||
%asmtmp = tail call { i32, i32 } asm "movl $0, %eax\0A\090:\0A\09test %eax, %eax\0A\09je 1f\0A\09movl %eax, $2\0A\09incl $2\0A\09lock\0A\09cmpxchgl $2, $0\0A\09jne 0b\0A\091:", "=*m,=&{ax},=&r,*m,~{dirflag},~{fpsr},~{flags},~{memory},~{cc}"(i32* %pw, i32* %pw) nounwind ; <{ i32, i32 }> [#uses=0]
|
||||
%asmtmp2 = tail call { i32, i32 } asm "movl $0, %edx\0A\090:\0A\09test %edx, %edx\0A\09je 1f\0A\09movl %edx, $2\0A\09incl $2\0A\09lock\0A\09cmpxchgl $2, $0\0A\09jne 0b\0A\091:", "=*m,=&{dx},=&r,*m,~{dirflag},~{fpsr},~{flags},~{memory},~{cc}"(i32* %pw, i32* %pw) nounwind ; <{ i32, i32 }> [#uses=1]
|
||||
%asmresult3 = extractvalue { i32, i32 } %asmtmp2, 0 ; <i32> [#uses=1]
|
||||
%1 = add i32 %asmresult3, %0 ; <i32> [#uses=1]
|
||||
ret i32 %1
|
||||
}
|
Loading…
Reference in New Issue
Block a user