add a gross hack to work around a problem that Argiris reported

on llvmdev: SRoA is introducing MMX datatypes like <1 x i64>,
which then cause random problems because the X86 backend is
producing mmx stuff without inserting proper emms calls.

In the short term, force off MMX datatypes.  In the long term,
the X86 backend should not select generic vector types to MMX
registers.  This is being worked on, but won't be done in time
for 2.8.  rdar://8380055


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112696 91177308-0d34-0410-b5e6-96231b3b80d8

test/Transforms/ScalarRepl/vector_promote.ll

@@ -85,3 +85,17 @@ define i32 @test5(float %X) {  ;; should turn into bitcast.
 ; CHECK-NEXT: ret i32
 }
 
+
+;; should not turn into <1 x i64> - It is a banned MMX datatype.
+;; rdar://8380055
+define i64 @test6(<2 x float> %X) {
+	%X_addr = alloca <2 x float>
+        store <2 x float> %X, <2 x float>* %X_addr
+	%P = bitcast <2 x float>* %X_addr to i64*
+	%tmp = load i64* %P
+	ret i64 %tmp
+; CHECK: @test6
+; CHECK-NEXT: bitcast <2 x float> %X to i64
+; CHECK-NEXT: ret i64
+}
+