6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-22 10:29:35 +00:00
Code Issues Projects Releases Wiki Activity

[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207506 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-04-29 07:58:02 +00:00
parent 6b7b725179
commit 91b10fb0e9
38 changed files with 390 additions and 392 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -75,10 +75,10 @@ class MipsAsmParser : public MCTargetAsmParser {
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
SmallVectorImpl<MCParsedAsmOperand *> &Operands, SmallVectorImpl<MCParsedAsmOperand *> &Operands,
MCStreamer &Out, unsigned &ErrorInfo, MCStreamer &Out, unsigned &ErrorInfo,
bool MatchingInlineAsm); bool MatchingInlineAsm) override;
/// Parse a register as used in CFI directives /// Parse a register as used in CFI directives
bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
bool ParseParenSuffix(StringRef Name, bool ParseParenSuffix(StringRef Name,
SmallVectorImpl<MCParsedAsmOperand *> &Operands); SmallVectorImpl<MCParsedAsmOperand *> &Operands);
@ -86,11 +86,11 @@ class MipsAsmParser : public MCTargetAsmParser {
bool ParseBracketSuffix(StringRef Name, bool ParseBracketSuffix(StringRef Name,
SmallVectorImpl<MCParsedAsmOperand *> &Operands); SmallVectorImpl<MCParsedAsmOperand *> &Operands);
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, bool
SMLoc NameLoc, ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand *> &Operands); SmallVectorImpl<MCParsedAsmOperand *> &Operands) override;
bool ParseDirective(AsmToken DirectiveID); bool ParseDirective(AsmToken DirectiveID) override;
MipsAsmParser::OperandMatchResultTy MipsAsmParser::OperandMatchResultTy
parseMemOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands); parseMemOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
@ -577,7 +577,7 @@ public:
addExpr(Inst, Expr); addExpr(Inst, Expr);
} }
bool isReg() const { bool isReg() const override {
// As a special case until we sort out the definition of div/divu, pretend // As a special case until we sort out the definition of div/divu, pretend
// that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly. // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
if (isGPRAsmReg() && RegIdx.Index == 0) if (isGPRAsmReg() && RegIdx.Index == 0)
@ -586,16 +586,16 @@ public:
return Kind == k_PhysRegister; return Kind == k_PhysRegister;
} }
bool isRegIdx() const { return Kind == k_RegisterIndex; } bool isRegIdx() const { return Kind == k_RegisterIndex; }
bool isImm() const { return Kind == k_Immediate; } bool isImm() const override { return Kind == k_Immediate; }
bool isConstantImm() const { bool isConstantImm() const {
return isImm() && dyn_cast<MCConstantExpr>(getImm()); return isImm() && dyn_cast<MCConstantExpr>(getImm());
} }
bool isToken() const { bool isToken() const override {
// Note: It's not possible to pretend that other operand kinds are tokens. // Note: It's not possible to pretend that other operand kinds are tokens.
// The matcher emitter checks tokens first. // The matcher emitter checks tokens first.
return Kind == k_Token; return Kind == k_Token;
} }
bool isMem() const { return Kind == k_Memory; } bool isMem() const override { return Kind == k_Memory; }
bool isInvNum() const { return Kind == k_Immediate; } bool isInvNum() const { return Kind == k_Immediate; }
bool isLSAImm() const { bool isLSAImm() const {
if (!isConstantImm()) if (!isConstantImm())
@ -609,7 +609,7 @@ public:
return StringRef(Tok.Data, Tok.Length); return StringRef(Tok.Data, Tok.Length);
} }
unsigned getReg() const { unsigned getReg() const override {
// As a special case until we sort out the definition of div/divu, pretend // As a special case until we sort out the definition of div/divu, pretend
// that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly. // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
if (Kind == k_RegisterIndex && RegIdx.Index == 0 && if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
@ -756,9 +756,9 @@ public:
} }
/// getStartLoc - Get the location of the first token of this operand. /// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const { return StartLoc; } SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Get the location of the last token of this operand. /// getEndLoc - Get the location of the last token of this operand.
SMLoc getEndLoc() const { return EndLoc; } SMLoc getEndLoc() const override { return EndLoc; }
virtual ~MipsOperand() { virtual ~MipsOperand() {
switch (Kind) { switch (Kind) {
@ -774,7 +774,7 @@ public:
} }
} }
virtual void print(raw_ostream &OS) const { void print(raw_ostream &OS) const override {
switch (Kind) { switch (Kind) {
case k_Immediate: case k_Immediate:
OS << "Imm<"; OS << "Imm<";

24
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -64,12 +64,12 @@ public:
} }
/// getInstruction - See MCDisassembler. /// getInstruction - See MCDisassembler.
virtual DecodeStatus getInstruction(MCInst &instr, DecodeStatus getInstruction(MCInst &instr,
uint64_t &size, uint64_t &size,
const MemoryObject &region, const MemoryObject &region,
uint64_t address, uint64_t address,
raw_ostream &vStream, raw_ostream &vStream,
raw_ostream &cStream) const; raw_ostream &cStream) const override;
}; };
@ -83,12 +83,12 @@ public:
MipsDisassemblerBase(STI, Ctx, bigEndian) {} MipsDisassemblerBase(STI, Ctx, bigEndian) {}
/// getInstruction - See MCDisassembler. /// getInstruction - See MCDisassembler.
virtual DecodeStatus getInstruction(MCInst &instr, DecodeStatus getInstruction(MCInst &instr,
uint64_t &size, uint64_t &size,
const MemoryObject &region, const MemoryObject &region,
uint64_t address, uint64_t address,
raw_ostream &vStream, raw_ostream &vStream,
raw_ostream &cStream) const; raw_ostream &cStream) const override;
}; };
} // end anonymous namespace } // end anonymous namespace

4
lib/Target/Mips/InstPrinter/MipsInstPrinter.h
View File

@ -85,8 +85,8 @@ public:
void printInstruction(const MCInst *MI, raw_ostream &O); void printInstruction(const MCInst *MI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo); static const char *getRegisterName(unsigned RegNo);
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; void printRegName(raw_ostream &OS, unsigned RegNo) const override;
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
bool printAliasInstr(const MCInst *MI, raw_ostream &OS); bool printAliasInstr(const MCInst *MI, raw_ostream &OS);

18
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
View File

@ -37,14 +37,14 @@ public:
: MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), : MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle),
Is64Bit(_is64Bit) {} Is64Bit(_is64Bit) {}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const; MCObjectWriter *createObjectWriter(raw_ostream &OS) const override;
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value, bool IsPCRel) const; uint64_t Value, bool IsPCRel) const override;
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const; const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
unsigned getNumFixupKinds() const { unsigned getNumFixupKinds() const override {
return Mips::NumTargetFixupKinds; return Mips::NumTargetFixupKinds;
} }
@ -55,7 +55,7 @@ public:
/// relaxation. /// relaxation.
/// ///
/// \param Inst - The instruction to test. /// \param Inst - The instruction to test.
bool mayNeedRelaxation(const MCInst &Inst) const { bool mayNeedRelaxation(const MCInst &Inst) const override {
return false; return false;
} }
@ -63,7 +63,7 @@ public:
/// fixup requires the associated instruction to be relaxed. /// fixup requires the associated instruction to be relaxed.
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
const MCRelaxableFragment *DF, const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const { const MCAsmLayout &Layout) const override {
// FIXME. // FIXME.
assert(0 && "RelaxInstruction() unimplemented"); assert(0 && "RelaxInstruction() unimplemented");
return false; return false;
@ -75,16 +75,16 @@ public:
/// \param Inst - The instruction to relax, which may be the same /// \param Inst - The instruction to relax, which may be the same
/// as the output. /// as the output.
/// \param [out] Res On return, the relaxed instruction. /// \param [out] Res On return, the relaxed instruction.
void relaxInstruction(const MCInst &Inst, MCInst &Res) const {} void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {}
/// @} /// @}
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
const MCFixup &Fixup, const MCFragment *DF, const MCFixup &Fixup, const MCFragment *DF,
const MCValue &Target, uint64_t &Value, const MCValue &Target, uint64_t &Value,
bool &IsResolved); bool &IsResolved) override;
}; // class MipsAsmBackend }; // class MipsAsmBackend

2
lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
View File

@ -20,7 +20,7 @@ namespace llvm {
class StringRef; class StringRef;
class MipsMCAsmInfo : public MCAsmInfoELF { class MipsMCAsmInfo : public MCAsmInfoELF {
virtual void anchor(); void anchor() override;
public: public:
explicit MipsMCAsmInfo(StringRef TT); explicit MipsMCAsmInfo(StringRef TT);
}; };

2
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
View File

@ -52,7 +52,7 @@ public:
void EncodeInstruction(const MCInst &MI, raw_ostream &OS, void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const; const MCSubtargetInfo &STI) const override;
// getBinaryCodeForInstr - TableGen'erated function for getting the // getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction. // binary encoding for an instruction.

10
lib/Target/Mips/MCTargetDesc/MipsMCExpr.h
View File

@ -46,16 +46,16 @@ public:
/// getSubExpr - Get the child of this expression. /// getSubExpr - Get the child of this expression.
const MCExpr *getSubExpr() const { return Expr; } const MCExpr *getSubExpr() const { return Expr; }
void PrintImpl(raw_ostream &OS) const; void PrintImpl(raw_ostream &OS) const override;
bool EvaluateAsRelocatableImpl(MCValue &Res, bool EvaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout) const; const MCAsmLayout *Layout) const override;
void AddValueSymbols(MCAssembler *) const; void AddValueSymbols(MCAssembler *) const override;
const MCSection *FindAssociatedSection() const { const MCSection *FindAssociatedSection() const override {
return getSubExpr()->FindAssociatedSection(); return getSubExpr()->FindAssociatedSection();
} }
// There are no TLS MipsMCExprs at the moment. // There are no TLS MipsMCExprs at the moment.
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {} void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
static bool classof(const MCExpr *E) { static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Target; return E->getKind() == MCExpr::Target;

3
lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
View File

@ -120,7 +120,8 @@ private:
public: public:
/// This function is the one used to emit instruction data into the ELF /// This function is the one used to emit instruction data into the ELF
/// streamer. We override it to mask dangerous instructions. /// streamer. We override it to mask dangerous instructions.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { void EmitInstruction(const MCInst &Inst,
const MCSubtargetInfo &STI) override {
// Sandbox indirect jumps. // Sandbox indirect jumps.
if (isIndirectJump(Inst)) { if (isIndirectJump(Inst)) {
if (PendingCall) if (PendingCall)

20
lib/Target/Mips/Mips16FrameLowering.h
View File

@ -24,27 +24,27 @@ public:
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. /// the function.
void emitPrologue(MachineFunction &MF) const; void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void eliminateCallFramePseudoInstr(MachineFunction &MF, void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const; MachineBasicBlock::iterator I) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
bool hasReservedCallFrame(const MachineFunction &MF) const; bool hasReservedCallFrame(const MachineFunction &MF) const override;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const; RegScavenger *RS) const override;
}; };
} // End llvm namespace } // End llvm namespace

4
lib/Target/Mips/Mips16HardFloat.h
View File

@ -34,11 +34,11 @@ public:
TM(TM_), Subtarget(TM.getSubtarget<MipsSubtarget>()) { TM(TM_), Subtarget(TM.getSubtarget<MipsSubtarget>()) {
} }
virtual const char *getPassName() const { const char *getPassName() const override {
return "MIPS16 Hard Float Pass"; return "MIPS16 Hard Float Pass";
} }
virtual bool runOnModule(Module &M); bool runOnModule(Module &M) override;
protected: protected:
/// Keep a pointer to the MipsSubtarget around so that we can make the right /// Keep a pointer to the MipsSubtarget around so that we can make the right

10
lib/Target/Mips/Mips16ISelDAGToDAG.h
View File

@ -28,16 +28,16 @@ private:
SDValue getMips16SPAliasReg(); SDValue getMips16SPAliasReg();
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
void getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg); void getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg);
virtual bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base, bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
SDValue &Offset, SDValue &Alias); SDValue &Offset, SDValue &Alias) override;
virtual std::pair<bool, SDNode*> selectNode(SDNode *Node); std::pair<bool, SDNode*> selectNode(SDNode *Node) override;
virtual void processFunctionAfterISel(MachineFunction &MF); void processFunctionAfterISel(MachineFunction &MF) override;
// Insert instructions to initialize the global base register in the // Insert instructions to initialize the global base register in the
// first MBB of the function. // first MBB of the function.

21
lib/Target/Mips/Mips16ISelLowering.h
View File

@ -21,17 +21,17 @@ namespace llvm {
public: public:
explicit Mips16TargetLowering(MipsTargetMachine &TM); explicit Mips16TargetLowering(MipsTargetMachine &TM);
virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace, bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
bool *Fast) const; bool *Fast) const override;
virtual MachineBasicBlock * MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const override;
private: private:
virtual bool bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, unsigned NextStackOffset,
unsigned NextStackOffset, const MipsFunctionInfo& FI) const override;
const MipsFunctionInfo& FI) const;
void setMips16HardFloatLibCalls(); void setMips16HardFloatLibCalls();
@ -41,11 +41,12 @@ namespace llvm {
const char *getMips16HelperFunction const char *getMips16HelperFunction
(Type* RetTy, ArgListTy &Args, bool &needHelper) const; (Type* RetTy, ArgListTy &Args, bool &needHelper) const;
virtual void void
getOpndList(SmallVectorImpl<SDValue> &Ops, getOpndList(SmallVectorImpl<SDValue> &Ops,
std::deque< std::pair<unsigned, SDValue> > &RegsToPass, std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const; CallLoweringInfo &CLI, SDValue Callee,
SDValue Chain) const override;
MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI,
MachineBasicBlock *BB) const; MachineBasicBlock *BB) const;

50
lib/Target/Mips/Mips16InstrInfo.h
View File

@ -25,46 +25,46 @@ class Mips16InstrInfo : public MipsInstrInfo {
public: public:
explicit Mips16InstrInfo(MipsTargetMachine &TM); explicit Mips16InstrInfo(MipsTargetMachine &TM);
virtual const MipsRegisterInfo &getRegisterInfo() const; const MipsRegisterInfo &getRegisterInfo() const override;
/// isLoadFromStackSlot - If the specified machine instruction is a direct /// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of /// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If /// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot. /// any side effects other than loading from the stack slot.
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const override;
/// isStoreToStackSlot - If the specified machine instruction is a direct /// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of /// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If /// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot. /// any side effects other than storing to the stack slot.
virtual unsigned isStoreToStackSlot(const MachineInstr *MI, unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const override;
virtual void copyPhysReg(MachineBasicBlock &MBB, void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL, MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const; bool KillSrc) const override;
virtual void storeRegToStack(MachineBasicBlock &MBB, void storeRegToStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex, unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
int64_t Offset) const; int64_t Offset) const override;
virtual void loadRegFromStack(MachineBasicBlock &MBB, void loadRegFromStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex, unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
int64_t Offset) const; int64_t Offset) const override;
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
virtual unsigned getOppositeBranchOpc(unsigned Opc) const; unsigned getOppositeBranchOpc(unsigned Opc) const override;
// Adjust SP by FrameSize bytes. Save RA, S0, S1 // Adjust SP by FrameSize bytes. Save RA, S0, S1
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
@ -104,9 +104,9 @@ public:
(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const; (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
unsigned getInlineAsmLength(const char *Str, unsigned getInlineAsmLength(const char *Str,
const MCAsmInfo &MAI) const; const MCAsmInfo &MAI) const override;
private: private:
virtual unsigned getAnalyzableBrOpc(unsigned Opc) const; unsigned getAnalyzableBrOpc(unsigned Opc) const override;
void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned Opc) const; unsigned Opc) const;

16
lib/Target/Mips/Mips16RegisterInfo.h
View File

@ -23,24 +23,24 @@ class Mips16RegisterInfo : public MipsRegisterInfo {
public: public:
Mips16RegisterInfo(const MipsSubtarget &Subtarget); Mips16RegisterInfo(const MipsSubtarget &Subtarget);
bool requiresRegisterScavenging(const MachineFunction &MF) const; bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const; bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
bool useFPForScavengingIndex(const MachineFunction &MF) const; bool useFPForScavengingIndex(const MachineFunction &MF) const override;
bool saveScavengerRegister(MachineBasicBlock &MBB, bool saveScavengerRegister(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
MachineBasicBlock::iterator &UseMI, MachineBasicBlock::iterator &UseMI,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
unsigned Reg) const; unsigned Reg) const override;
virtual const TargetRegisterClass *intRegClass(unsigned Size) const; const TargetRegisterClass *intRegClass(unsigned Size) const override;
private: private:
virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
int FrameIndex, uint64_t StackSize, int FrameIndex, uint64_t StackSize,
int64_t SPOffset) const; int64_t SPOffset) const override;
}; };
} // end namespace llvm } // end namespace llvm

26
lib/Target/Mips/MipsAsmPrinter.h
View File

@ -87,13 +87,13 @@ public:
Subtarget = &TM.getSubtarget<MipsSubtarget>(); Subtarget = &TM.getSubtarget<MipsSubtarget>();
} }
virtual const char *getPassName() const { const char *getPassName() const override {
return "Mips Assembly Printer"; return "Mips Assembly Printer";
} }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
virtual void EmitConstantPool() override { void EmitConstantPool() override {
bool UsingConstantPools = bool UsingConstantPools =
(Subtarget->inMips16Mode() && Subtarget->useConstantIslands()); (Subtarget->inMips16Mode() && Subtarget->useConstantIslands());
if (!UsingConstantPools) if (!UsingConstantPools)
@ -101,21 +101,21 @@ public:
// we emit constant pools customly! // we emit constant pools customly!
} }
void EmitInstruction(const MachineInstr *MI); void EmitInstruction(const MachineInstr *MI) override;
void printSavedRegsBitmask(); void printSavedRegsBitmask();
void emitFrameDirective(); void emitFrameDirective();
const char *getCurrentABIString() const; const char *getCurrentABIString() const;
virtual void EmitFunctionEntryLabel(); void EmitFunctionEntryLabel() override;
virtual void EmitFunctionBodyStart(); void EmitFunctionBodyStart() override;
virtual void EmitFunctionBodyEnd(); void EmitFunctionBodyEnd() override;
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock* bool isBlockOnlyReachableByFallthrough(
MBB) const; const MachineBasicBlock* MBB) const override;
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode, unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O); raw_ostream &O) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode, unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O); raw_ostream &O) override;
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
void printUnsignedImm8(const MachineInstr *MI, int opNum, raw_ostream &O); void printUnsignedImm8(const MachineInstr *MI, int opNum, raw_ostream &O);
@ -123,8 +123,8 @@ public:
void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O); void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O);
void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
const char *Modifier = nullptr); const char *Modifier = nullptr);
void EmitStartOfAsmFile(Module &M); void EmitStartOfAsmFile(Module &M) override;
void EmitEndOfAsmFile(Module &M); void EmitEndOfAsmFile(Module &M) override;
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
}; };
} }

6
lib/Target/Mips/MipsCodeEmitter.cpp
View File

@ -57,7 +57,7 @@ class MipsCodeEmitter : public MachineFunctionPass {
const std::vector<MachineJumpTableEntry> *MJTEs; const std::vector<MachineJumpTableEntry> *MJTEs;
bool IsPIC; bool IsPIC;
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineModuleInfo> (); AU.addRequired<MachineModuleInfo> ();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
@ -70,9 +70,9 @@ public:
TM(tm), MCE(mce), MCPEs(nullptr), MJTEs(nullptr), TM(tm), MCE(mce), MCPEs(nullptr), MJTEs(nullptr),
IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
virtual const char *getPassName() const { const char *getPassName() const override {
return "Mips Machine Code Emitter"; return "Mips Machine Code Emitter";
} }

4
lib/Target/Mips/MipsConstantIslandPass.cpp
View File

@ -371,11 +371,11 @@ namespace {
STI(&TM.getSubtarget<MipsSubtarget>()), MF(nullptr), MCP(nullptr), STI(&TM.getSubtarget<MipsSubtarget>()), MF(nullptr), MCP(nullptr),
PrescannedForConstants(false){} PrescannedForConstants(false){}
virtual const char *getPassName() const { const char *getPassName() const override {
return "Mips Constant Islands"; return "Mips Constant Islands";
} }
bool runOnMachineFunction(MachineFunction &F); bool runOnMachineFunction(MachineFunction &F) override;
void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs); void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);
CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI); CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);

12
lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -124,7 +124,7 @@ namespace {
public: public:
NoMemInstr() : InspectMemInstr(true) {} NoMemInstr() : InspectMemInstr(true) {}
private: private:
virtual bool hasHazard_(const MachineInstr &MI) { return true; } bool hasHazard_(const MachineInstr &MI) override { return true; }
}; };
/// This subclass accepts loads from stacks and constant loads. /// This subclass accepts loads from stacks and constant loads.
@ -132,7 +132,7 @@ namespace {
public: public:
LoadFromStackOrConst() : InspectMemInstr(false) {} LoadFromStackOrConst() : InspectMemInstr(false) {}
private: private:
virtual bool hasHazard_(const MachineInstr &MI); bool hasHazard_(const MachineInstr &MI) override;
}; };
/// This subclass uses memory dependence information to determine whether a /// This subclass uses memory dependence information to determine whether a
@ -144,7 +144,7 @@ namespace {
private: private:
typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType; typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
virtual bool hasHazard_(const MachineInstr &MI); bool hasHazard_(const MachineInstr &MI) override;
/// Update Defs and Uses. Return true if there exist dependences that /// Update Defs and Uses. Return true if there exist dependences that
/// disqualify the delay slot candidate between V and values in Uses and /// disqualify the delay slot candidate between V and values in Uses and
@ -168,11 +168,11 @@ namespace {
Filler(TargetMachine &tm) Filler(TargetMachine &tm)
: MachineFunctionPass(ID), TM(tm) { } : MachineFunctionPass(ID), TM(tm) { }
virtual const char *getPassName() const { const char *getPassName() const override {
return "Mips Delay Slot Filler"; return "Mips Delay Slot Filler";
} }
bool runOnMachineFunction(MachineFunction &F) { bool runOnMachineFunction(MachineFunction &F) override {
bool Changed = false; bool Changed = false;
for (MachineFunction::iterator FI = F.begin(), FE = F.end(); for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI) FI != FE; ++FI)
@ -180,7 +180,7 @@ namespace {
return Changed; return Changed;
} }
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineBranchProbabilityInfo>(); AU.addRequired<MachineBranchProbabilityInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }

2
lib/Target/Mips/MipsFrameLowering.h
View File

@ -32,7 +32,7 @@ public:
static const MipsFrameLowering *create(MipsTargetMachine &TM, static const MipsFrameLowering *create(MipsTargetMachine &TM,
const MipsSubtarget &ST); const MipsSubtarget &ST);
bool hasFP(const MachineFunction &MF) const; bool hasFP(const MachineFunction &MF) const override;
protected: protected:
uint64_t estimateStackSize(const MachineFunction &MF) const; uint64_t estimateStackSize(const MachineFunction &MF) const;

12
lib/Target/Mips/MipsISelDAGToDAG.h
View File

@ -35,11 +35,11 @@ public:
: SelectionDAGISel(TM), Subtarget(TM.getSubtarget<MipsSubtarget>()) {} : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<MipsSubtarget>()) {}
// Pass Name // Pass Name
virtual const char *getPassName() const { const char *getPassName() const override {
return "MIPS DAG->DAG Pattern Instruction Selection"; return "MIPS DAG->DAG Pattern Instruction Selection";
} }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
protected: protected:
SDNode *getGlobalBaseReg(); SDNode *getGlobalBaseReg();
@ -110,7 +110,7 @@ private:
/// starting at bit zero. /// starting at bit zero.
virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const; virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const;
virtual SDNode *Select(SDNode *N); SDNode *Select(SDNode *N) override;
virtual std::pair<bool, SDNode*> selectNode(SDNode *Node) = 0; virtual std::pair<bool, SDNode*> selectNode(SDNode *Node) = 0;
@ -121,9 +121,9 @@ private:
virtual void processFunctionAfterISel(MachineFunction &MF) = 0; virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode, char ConstraintCode,
std::vector<SDValue> &OutOps); std::vector<SDValue> &OutOps) override;
}; };
/// createMipsISelDag - This pass converts a legalized DAG into a /// createMipsISelDag - This pass converts a legalized DAG into a

87
lib/Target/Mips/MipsISelLowering.h
View File

@ -223,32 +223,33 @@ namespace llvm {
FastISel *createFastISel(FunctionLoweringInfo &funcInfo, FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo) const override; const TargetLibraryInfo *libInfo) const override;
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
virtual void LowerOperationWrapper(SDNode *N, void LowerOperationWrapper(SDNode *N,
SmallVectorImpl<SDValue> &Results, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const; SelectionDAG &DAG) const override;
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
/// ReplaceNodeResults - Replace the results of node with an illegal result /// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code. /// type with new values built out of custom code.
/// ///
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const; SelectionDAG &DAG) const override;
/// getTargetNodeName - This method returns the name of a target specific /// getTargetNodeName - This method returns the name of a target specific
// DAG node. // DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const; const char *getTargetNodeName(unsigned Opcode) const override;
/// getSetCCResultType - get the ISD::SETCC result ValueType /// getSetCCResultType - get the ISD::SETCC result ValueType
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
virtual MachineBasicBlock * MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const override;
struct LTStr { struct LTStr {
bool operator()(const char *S1, const char *S2) const { bool operator()(const char *S1, const char *S2) const {
@ -528,41 +529,39 @@ namespace llvm {
void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC, void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
SDValue Chain, SDLoc DL, SelectionDAG &DAG) const; SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
virtual SDValue SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG, SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const override;
SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
SDValue Arg, SDLoc DL, bool IsTailCall, SDValue Arg, SDLoc DL, bool IsTailCall,
SelectionDAG &DAG) const; SelectionDAG &DAG) const;
virtual SDValue SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const override;
SmallVectorImpl<SDValue> &InVals) const;
virtual bool bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const override;
LLVMContext &Context) const;
virtual SDValue SDValue LowerReturn(SDValue Chain,
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<SDValue> &OutVals, SDLoc dl, SelectionDAG &DAG) const override;
SDLoc dl, SelectionDAG &DAG) const;
// Inline asm support // Inline asm support
ConstraintType getConstraintType(const std::string &Constraint) const; ConstraintType
getConstraintType(const std::string &Constraint) const override;
/// Examine constraint string and operand type and determine a weight value. /// Examine constraint string and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type. /// The operand object must already have been set up with the operand type.
ConstraintWeight getSingleConstraintMatchWeight( ConstraintWeight getSingleConstraintMatchWeight(
AsmOperandInfo &info, const char *constraint) const; AsmOperandInfo &info, const char *constraint) const override;
/// This function parses registers that appear in inline-asm constraints. /// This function parses registers that appear in inline-asm constraints.
/// It returns pair (0, 0) on failure. /// It returns pair (0, 0) on failure.
@ -571,33 +570,33 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*> std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const; MVT VT) const override;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
/// true it means one of the asm constraint of the inline asm instruction /// true it means one of the asm constraint of the inline asm instruction
/// being processed is 'm'. /// being processed is 'm'.
virtual void LowerAsmOperandForConstraint(SDValue Op, void LowerAsmOperandForConstraint(SDValue Op,
std::string &Constraint, std::string &Constraint,
std::vector<SDValue> &Ops, std::vector<SDValue> &Ops,
SelectionDAG &DAG) const; SelectionDAG &DAG) const override;
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
unsigned SrcAlign, unsigned SrcAlign,
bool IsMemset, bool ZeroMemset, bool IsMemset, bool ZeroMemset,
bool MemcpyStrSrc, bool MemcpyStrSrc,
MachineFunction &MF) const; MachineFunction &MF) const override;
/// isFPImmLegal - Returns true if the target can instruction select the /// isFPImmLegal - Returns true if the target can instruction select the
/// specified FP immediate natively. If false, the legalizer will /// specified FP immediate natively. If false, the legalizer will
/// materialize the FP immediate as a load from a constant pool. /// materialize the FP immediate as a load from a constant pool.
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
virtual unsigned getJumpTableEncoding() const; unsigned getJumpTableEncoding() const override;
MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
unsigned Size, unsigned BinOpcode, bool Nand = false) const; unsigned Size, unsigned BinOpcode, bool Nand = false) const;

46
lib/Target/Mips/MipsInstrInfo.h
View File

@ -47,20 +47,20 @@ public:
static const MipsInstrInfo *create(MipsTargetMachine &TM); static const MipsInstrInfo *create(MipsTargetMachine &TM);
/// Branch Analysis /// Branch Analysis
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond, SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const; bool AllowModify) const override;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const; DebugLoc DL) const override;
virtual bool
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
@ -69,8 +69,8 @@ public:
SmallVectorImpl<MachineInstr*> &BranchInstrs) const; SmallVectorImpl<MachineInstr*> &BranchInstrs) const;
/// Insert nop instruction when hazard condition is found /// Insert nop instruction when hazard condition is found
virtual void insertNoop(MachineBasicBlock &MBB, void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const; MachineBasicBlock::iterator MI) const override;
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should /// such, whenever a client has an instance of instruction info, it should
@ -83,19 +83,19 @@ public:
/// Return the number of bytes of code the specified instruction may be. /// Return the number of bytes of code the specified instruction may be.
unsigned GetInstSizeInBytes(const MachineInstr *MI) const; unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex, unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const override {
storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
} }
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex, unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const override {
loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
} }

14
lib/Target/Mips/MipsJITInfo.h
View File

@ -37,26 +37,26 @@ class MipsJITInfo : public TargetJITInfo {
/// overwriting OLD with a branch to NEW. This is used for self-modifying /// overwriting OLD with a branch to NEW. This is used for self-modifying
/// code. /// code.
/// ///
virtual void replaceMachineCodeForFunction(void *Old, void *New); void replaceMachineCodeForFunction(void *Old, void *New) override;
// getStubLayout - Returns the size and alignment of the largest call stub // getStubLayout - Returns the size and alignment of the largest call stub
// on Mips. // on Mips.
virtual StubLayout getStubLayout(); StubLayout getStubLayout() override;
/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
/// small native function that simply calls the function at the specified /// small native function that simply calls the function at the specified
/// address. /// address.
virtual void *emitFunctionStub(const Function *F, void *Fn, void *emitFunctionStub(const Function *F, void *Fn,
JITCodeEmitter &JCE); JITCodeEmitter &JCE) override;
/// getLazyResolverFunction - Expose the lazy resolver to the JIT. /// getLazyResolverFunction - Expose the lazy resolver to the JIT.
virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn); LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
/// relocate - Before the JIT can run a block of code that has been emitted, /// relocate - Before the JIT can run a block of code that has been emitted,
/// it must rewrite the code to contain the actual addresses of any /// it must rewrite the code to contain the actual addresses of any
/// referenced global symbols. /// referenced global symbols.
virtual void relocate(void *Function, MachineRelocation *MR, void relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char *GOTBase); unsigned NumRelocs, unsigned char *GOTBase) override;
/// Initialize - Initialize internal stage for the function being JITted. /// Initialize - Initialize internal stage for the function being JITted.
void Initialize(const MachineFunction &MF, bool isPIC, void Initialize(const MachineFunction &MF, bool isPIC,

4
lib/Target/Mips/MipsLongBranch.cpp
View File

@ -69,11 +69,11 @@ namespace {
ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()), ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()),
LongBranchSeqSize(!IsPIC ? 2 : (ABI == MipsSubtarget::N64 ? 13 : 9)) {} LongBranchSeqSize(!IsPIC ? 2 : (ABI == MipsSubtarget::N64 ? 13 : 9)) {}
virtual const char *getPassName() const { const char *getPassName() const override {
return "Mips Long Branch"; return "Mips Long Branch";
} }
bool runOnMachineFunction(MachineFunction &F); bool runOnMachineFunction(MachineFunction &F) override;
private: private:
void splitMBB(MachineBasicBlock *MBB); void splitMBB(MachineBasicBlock *MBB);

8
lib/Target/Mips/MipsMachineFunction.h
View File

@ -37,12 +37,12 @@ class MipsCallEntry : public PseudoSourceValue {
public: public:
explicit MipsCallEntry(const StringRef &N); explicit MipsCallEntry(const StringRef &N);
explicit MipsCallEntry(const GlobalValue *V); explicit MipsCallEntry(const GlobalValue *V);
virtual bool isConstant(const MachineFrameInfo *) const; bool isConstant(const MachineFrameInfo *) const override;
virtual bool isAliased(const MachineFrameInfo *) const; bool isAliased(const MachineFrameInfo *) const override;
virtual bool mayAlias(const MachineFrameInfo *) const; bool mayAlias(const MachineFrameInfo *) const override;
private: private:
virtual void printCustom(raw_ostream &O) const; void printCustom(raw_ostream &O) const override;
#ifndef NDEBUG #ifndef NDEBUG
std::string Name; std::string Name;
const GlobalValue *Val; const GlobalValue *Val;

8
lib/Target/Mips/MipsModuleISelDAGToDAG.h
View File

@ -41,15 +41,11 @@ public:
TM(TM_), Subtarget(TM.getSubtarget<MipsSubtarget>()) {} TM(TM_), Subtarget(TM.getSubtarget<MipsSubtarget>()) {}
// Pass Name // Pass Name
virtual const char *getPassName() const { const char *getPassName() const override {
return "MIPS DAG->DAG Pattern Instruction Selection"; return "MIPS DAG->DAG Pattern Instruction Selection";
} }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
virtual SDNode *Select(SDNode *N) {
llvm_unreachable("unexpected");
}
protected: protected:
/// Keep a pointer to the MipsSubtarget around so that we can make the right /// Keep a pointer to the MipsSubtarget around so that we can make the right

6
lib/Target/Mips/MipsOptimizePICCall.cpp
View File

@ -61,11 +61,11 @@ class OptimizePICCall : public MachineFunctionPass {
public: public:
OptimizePICCall(TargetMachine &tm) : MachineFunctionPass(ID) {} OptimizePICCall(TargetMachine &tm) : MachineFunctionPass(ID) {}
virtual const char *getPassName() const { return "Mips OptimizePICCall"; } const char *getPassName() const override { return "Mips OptimizePICCall"; }
bool runOnMachineFunction(MachineFunction &F); bool runOnMachineFunction(MachineFunction &F) override;
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineDominatorTree>(); AU.addRequired<MachineDominatorTree>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }

4
lib/Target/Mips/MipsOs16.h
View File

@ -34,11 +34,11 @@ public:
} }
virtual const char *getPassName() const { const char *getPassName() const override {
return "MIPS Os16 Optimization"; return "MIPS Os16 Optimization";
} }
virtual bool runOnModule(Module &M); bool runOnModule(Module &M) override;
}; };

19
lib/Target/Mips/MipsRegisterInfo.h
View File

@ -43,30 +43,31 @@ public:
/// Code Generation virtual methods... /// Code Generation virtual methods...
const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF, const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
unsigned Kind) const; unsigned Kind) const override;
unsigned getRegPressureLimit(const TargetRegisterClass *RC, unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const; MachineFunction &MF) const override;
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const; const MCPhysReg *
const uint32_t *getCallPreservedMask(CallingConv::ID) const; getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
static const uint32_t *getMips16RetHelperMask(); static const uint32_t *getMips16RetHelperMask();
BitVector getReservedRegs(const MachineFunction &MF) const; BitVector getReservedRegs(const MachineFunction &MF) const override;
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const; bool requiresRegisterScavenging(const MachineFunction &MF) const override;
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
/// Stack Frame Processing Methods /// Stack Frame Processing Methods
void eliminateFrameIndex(MachineBasicBlock::iterator II, void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum, int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const; RegScavenger *RS = nullptr) const override;
void processFunctionBeforeFrameFinalized(MachineFunction &MF, void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = nullptr) const; RegScavenger *RS = nullptr) const;
/// Debug information queries. /// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const; unsigned getFrameRegister(const MachineFunction &MF) const override;
/// \brief Return GPR register class. /// \brief Return GPR register class.
virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0; virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;

14
lib/Target/Mips/MipsSEFrameLowering.h
View File

@ -25,22 +25,22 @@ public:
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. /// the function.
void emitPrologue(MachineFunction &MF) const; void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void eliminateCallFramePseudoInstr(MachineFunction &MF, void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const; MachineBasicBlock::iterator I) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
bool hasReservedCallFrame(const MachineFunction &MF) const; bool hasReservedCallFrame(const MachineFunction &MF) const override;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const; RegScavenger *RS) const override;
unsigned ehDataReg(unsigned I) const; unsigned ehDataReg(unsigned I) const;
}; };

66
lib/Target/Mips/MipsSEISelDAGToDAG.h
View File

@ -25,7 +25,7 @@ public:
private: private:
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
MachineFunction &MF); MachineFunction &MF);
@ -44,66 +44,66 @@ private:
bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset, bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
unsigned OffsetBits) const; unsigned OffsetBits) const;
virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base, bool selectAddrRegImm(SDValue Addr, SDValue &Base,
SDValue &Offset) const; SDValue &Offset) const override;
virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base, bool selectAddrRegReg(SDValue Addr, SDValue &Base,
SDValue &Offset) const; SDValue &Offset) const override;
virtual bool selectAddrDefault(SDValue Addr, SDValue &Base, bool selectAddrDefault(SDValue Addr, SDValue &Base,
SDValue &Offset) const; SDValue &Offset) const override;
virtual bool selectIntAddr(SDValue Addr, SDValue &Base, bool selectIntAddr(SDValue Addr, SDValue &Base,
SDValue &Offset) const; SDValue &Offset) const override;
virtual bool selectAddrRegImm10(SDValue Addr, SDValue &Base, bool selectAddrRegImm10(SDValue Addr, SDValue &Base,
SDValue &Offset) const; SDValue &Offset) const;
virtual bool selectAddrRegImm12(SDValue Addr, SDValue &Base, bool selectAddrRegImm12(SDValue Addr, SDValue &Base,
SDValue &Offset) const; SDValue &Offset) const;
virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base, bool selectIntAddrMM(SDValue Addr, SDValue &Base,
SDValue &Offset) const; SDValue &Offset) const override;
virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base, bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
SDValue &Offset) const; SDValue &Offset) const override;
/// \brief Select constant vector splats. /// \brief Select constant vector splats.
virtual bool selectVSplat(SDNode *N, APInt &Imm) const; bool selectVSplat(SDNode *N, APInt &Imm) const override;
/// \brief Select constant vector splats whose value fits in a given integer. /// \brief Select constant vector splats whose value fits in a given integer.
virtual bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed, bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
unsigned ImmBitSize) const; unsigned ImmBitSize) const;
/// \brief Select constant vector splats whose value fits in a uimm1. /// \brief Select constant vector splats whose value fits in a uimm1.
virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const; bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm2. /// \brief Select constant vector splats whose value fits in a uimm2.
virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const; bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm3. /// \brief Select constant vector splats whose value fits in a uimm3.
virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const; bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm4. /// \brief Select constant vector splats whose value fits in a uimm4.
virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const; bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm5. /// \brief Select constant vector splats whose value fits in a uimm5.
virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const; bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm6. /// \brief Select constant vector splats whose value fits in a uimm6.
virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const; bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm8. /// \brief Select constant vector splats whose value fits in a uimm8.
virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const; bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a simm5. /// \brief Select constant vector splats whose value fits in a simm5.
virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const; bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value is a power of 2. /// \brief Select constant vector splats whose value is a power of 2.
virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const; bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value is the inverse of a /// \brief Select constant vector splats whose value is the inverse of a
/// power of 2. /// power of 2.
virtual bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const; bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value is a run of set bits /// \brief Select constant vector splats whose value is a run of set bits
/// ending at the most significant bit /// ending at the most significant bit
virtual bool selectVSplatMaskL(SDValue N, SDValue &Imm) const; bool selectVSplatMaskL(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value is a run of set bits /// \brief Select constant vector splats whose value is a run of set bits
/// starting at bit zero. /// starting at bit zero.
virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const; bool selectVSplatMaskR(SDValue N, SDValue &Imm) const override;
virtual std::pair<bool, SDNode*> selectNode(SDNode *Node); std::pair<bool, SDNode*> selectNode(SDNode *Node) override;
virtual void processFunctionAfterISel(MachineFunction &MF); void processFunctionAfterISel(MachineFunction &MF) override;
// Insert instructions to initialize the global base register in the // Insert instructions to initialize the global base register in the
// first MBB of the function. // first MBB of the function.

27
lib/Target/Mips/MipsSEISelLowering.h
View File

@ -33,19 +33,20 @@ namespace llvm {
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0, bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0,
bool *Fast = nullptr) const override; bool *Fast = nullptr) const override;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
virtual MachineBasicBlock * MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const override;
virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
EVT VT) const { EVT VT) const override {
return false; return false;
} }
virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { const TargetRegisterClass *getRepRegClassFor(MVT VT) const override {
if (VT == MVT::Untyped) if (VT == MVT::Untyped)
return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass : return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
&Mips::ACC64RegClass; &Mips::ACC64RegClass;
@ -54,16 +55,16 @@ namespace llvm {
} }
private: private:
virtual bool bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, unsigned NextStackOffset,
unsigned NextStackOffset, const MipsFunctionInfo& FI) const override;
const MipsFunctionInfo& FI) const;
virtual void void
getOpndList(SmallVectorImpl<SDValue> &Ops, getOpndList(SmallVectorImpl<SDValue> &Ops,
std::deque< std::pair<unsigned, SDValue> > &RegsToPass, std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const; CallLoweringInfo &CLI, SDValue Callee,
SDValue Chain) const override;
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;

48
lib/Target/Mips/MipsSEInstrInfo.h
View File

@ -26,46 +26,46 @@ class MipsSEInstrInfo : public MipsInstrInfo {
public: public:
explicit MipsSEInstrInfo(MipsTargetMachine &TM); explicit MipsSEInstrInfo(MipsTargetMachine &TM);
virtual const MipsRegisterInfo &getRegisterInfo() const; const MipsRegisterInfo &getRegisterInfo() const override;
/// isLoadFromStackSlot - If the specified machine instruction is a direct /// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of /// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If /// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot. /// any side effects other than loading from the stack slot.
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const override;
/// isStoreToStackSlot - If the specified machine instruction is a direct /// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of /// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If /// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot. /// any side effects other than storing to the stack slot.
virtual unsigned isStoreToStackSlot(const MachineInstr *MI, unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const override;
virtual void copyPhysReg(MachineBasicBlock &MBB, void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL, MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const; bool KillSrc) const override;
virtual void storeRegToStack(MachineBasicBlock &MBB, void storeRegToStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, int FrameIndex, unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
int64_t Offset) const; int64_t Offset) const override;
virtual void loadRegFromStack(MachineBasicBlock &MBB, void loadRegFromStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex, unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
int64_t Offset) const; int64_t Offset) const override;
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
virtual unsigned getOppositeBranchOpc(unsigned Opc) const; unsigned getOppositeBranchOpc(unsigned Opc) const override;
/// Adjust SP by Amount bytes. /// Adjust SP by Amount bytes.
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
@ -79,7 +79,7 @@ public:
unsigned *NewImm) const; unsigned *NewImm) const;
private: private:
virtual unsigned getAnalyzableBrOpc(unsigned Opc) const; unsigned getAnalyzableBrOpc(unsigned Opc) const override;
void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned Opc) const; unsigned Opc) const;

12
lib/Target/Mips/MipsSERegisterInfo.h
View File

@ -24,16 +24,16 @@ class MipsSERegisterInfo : public MipsRegisterInfo {
public: public:
MipsSERegisterInfo(const MipsSubtarget &Subtarget); MipsSERegisterInfo(const MipsSubtarget &Subtarget);
bool requiresRegisterScavenging(const MachineFunction &MF) const; bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const; bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
virtual const TargetRegisterClass *intRegClass(unsigned Size) const; const TargetRegisterClass *intRegClass(unsigned Size) const override;
private: private:
virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
int FrameIndex, uint64_t StackSize, int FrameIndex, uint64_t StackSize,
int64_t SPOffset) const; int64_t SPOffset) const override;
}; };
} // end namespace llvm } // end namespace llvm

6
lib/Target/Mips/MipsSubtarget.h
View File

@ -130,9 +130,9 @@ protected:
Triple TargetTriple; Triple TargetTriple;
public: public:
virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
AntiDepBreakMode& Mode, AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const; RegClassVector& CriticalPathRCs) const override;
/// Only O32 and EABI supported right now. /// Only O32 and EABI supported right now.
bool isABI_EABI() const { return MipsABI == EABI; } bool isABI_EABI() const { return MipsABI == EABI; }

10
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -171,12 +171,12 @@ public:
return *getMipsTargetMachine().getSubtargetImpl(); return *getMipsTargetMachine().getSubtargetImpl();
} }
virtual void addIRPasses(); void addIRPasses() override;
virtual bool addInstSelector(); bool addInstSelector() override;
virtual void addMachineSSAOptimization(); void addMachineSSAOptimization() override;
virtual bool addPreEmitPass(); bool addPreEmitPass() override;
virtual bool addPreRegAlloc(); bool addPreRegAlloc() override;
}; };
} // namespace } // namespace

25
lib/Target/Mips/MipsTargetMachine.h
View File

@ -55,39 +55,38 @@ public:
virtual ~MipsTargetMachine() {} virtual ~MipsTargetMachine() {}
virtual void addAnalysisPasses(PassManagerBase &PM); void addAnalysisPasses(PassManagerBase &PM) override;
virtual const MipsInstrInfo *getInstrInfo() const const MipsInstrInfo *getInstrInfo() const override
{ return InstrInfo.get(); } { return InstrInfo.get(); }
virtual const TargetFrameLowering *getFrameLowering() const const TargetFrameLowering *getFrameLowering() const override
{ return FrameLowering.get(); } { return FrameLowering.get(); }
virtual const MipsSubtarget *getSubtargetImpl() const const MipsSubtarget *getSubtargetImpl() const override
{ return &Subtarget; } { return &Subtarget; }
virtual const DataLayout *getDataLayout() const const DataLayout *getDataLayout() const override
{ return &DL;} { return &DL;}
virtual const InstrItineraryData *getInstrItineraryData() const { const InstrItineraryData *getInstrItineraryData() const override {
return Subtarget.inMips16Mode() ? nullptr : &InstrItins; return Subtarget.inMips16Mode() ? nullptr : &InstrItins;
} }
virtual MipsJITInfo *getJITInfo() MipsJITInfo *getJITInfo() override { return &JITInfo; }
{ return &JITInfo; }
virtual const MipsRegisterInfo *getRegisterInfo() const { const MipsRegisterInfo *getRegisterInfo() const override {
return &InstrInfo->getRegisterInfo(); return &InstrInfo->getRegisterInfo();
} }
virtual const MipsTargetLowering *getTargetLowering() const { const MipsTargetLowering *getTargetLowering() const override {
return TLInfo.get(); return TLInfo.get();
} }
virtual const MipsSelectionDAGInfo* getSelectionDAGInfo() const { const MipsSelectionDAGInfo* getSelectionDAGInfo() const override {
return &TSInfo; return &TSInfo;
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE); bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
// Set helper classes // Set helper classes
void setHelperClassesMips16(); void setHelperClassesMips16();

104
lib/Target/Mips/MipsTargetStreamer.h
View File

@ -55,34 +55,34 @@ class MipsTargetAsmStreamer : public MipsTargetStreamer {
public: public:
MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS); MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
virtual void emitDirectiveSetMicroMips(); void emitDirectiveSetMicroMips() override;
virtual void emitDirectiveSetNoMicroMips(); void emitDirectiveSetNoMicroMips() override;
virtual void emitDirectiveSetMips16(); void emitDirectiveSetMips16() override;
virtual void emitDirectiveSetNoMips16(); void emitDirectiveSetNoMips16() override;
virtual void emitDirectiveSetReorder(); void emitDirectiveSetReorder() override;
virtual void emitDirectiveSetNoReorder(); void emitDirectiveSetNoReorder() override;
virtual void emitDirectiveSetMacro(); void emitDirectiveSetMacro() override;
virtual void emitDirectiveSetNoMacro(); void emitDirectiveSetNoMacro() override;
virtual void emitDirectiveSetAt(); void emitDirectiveSetAt() override;
virtual void emitDirectiveSetNoAt(); void emitDirectiveSetNoAt() override;
virtual void emitDirectiveEnd(StringRef Name); void emitDirectiveEnd(StringRef Name) override;
virtual void emitDirectiveEnt(const MCSymbol &Symbol); void emitDirectiveEnt(const MCSymbol &Symbol) override;
virtual void emitDirectiveAbiCalls(); void emitDirectiveAbiCalls() override;
virtual void emitDirectiveNaN2008(); void emitDirectiveNaN2008() override;
virtual void emitDirectiveNaNLegacy(); void emitDirectiveNaNLegacy() override;
virtual void emitDirectiveOptionPic0(); void emitDirectiveOptionPic0() override;
virtual void emitDirectiveOptionPic2(); void emitDirectiveOptionPic2() override;
virtual void emitFrame(unsigned StackReg, unsigned StackSize, void emitFrame(unsigned StackReg, unsigned StackSize,
unsigned ReturnReg); unsigned ReturnReg) override;
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff); void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff); void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
virtual void emitDirectiveSetMips32R2(); void emitDirectiveSetMips32R2() override;
virtual void emitDirectiveSetMips64(); void emitDirectiveSetMips64() override;
virtual void emitDirectiveSetMips64R2(); void emitDirectiveSetMips64R2() override;
virtual void emitDirectiveSetDsp(); void emitDirectiveSetDsp() override;
}; };
// This part is for ELF object output // This part is for ELF object output
@ -96,38 +96,38 @@ public:
MCELFStreamer &getStreamer(); MCELFStreamer &getStreamer();
MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI); MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
virtual void emitLabel(MCSymbol *Symbol) override; void emitLabel(MCSymbol *Symbol) override;
virtual void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override; void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override;
void finish() override; void finish() override;
virtual void emitDirectiveSetMicroMips(); void emitDirectiveSetMicroMips() override;
virtual void emitDirectiveSetNoMicroMips(); void emitDirectiveSetNoMicroMips() override;
virtual void emitDirectiveSetMips16(); void emitDirectiveSetMips16() override;
virtual void emitDirectiveSetNoMips16(); void emitDirectiveSetNoMips16() override;
virtual void emitDirectiveSetReorder(); void emitDirectiveSetReorder() override;
virtual void emitDirectiveSetNoReorder(); void emitDirectiveSetNoReorder() override;
virtual void emitDirectiveSetMacro(); void emitDirectiveSetMacro() override;
virtual void emitDirectiveSetNoMacro(); void emitDirectiveSetNoMacro() override;
virtual void emitDirectiveSetAt(); void emitDirectiveSetAt() override;
virtual void emitDirectiveSetNoAt(); void emitDirectiveSetNoAt() override;
virtual void emitDirectiveEnd(StringRef Name); void emitDirectiveEnd(StringRef Name) override;
virtual void emitDirectiveEnt(const MCSymbol &Symbol); void emitDirectiveEnt(const MCSymbol &Symbol) override;
virtual void emitDirectiveAbiCalls(); void emitDirectiveAbiCalls() override;
virtual void emitDirectiveNaN2008(); void emitDirectiveNaN2008() override;
virtual void emitDirectiveNaNLegacy(); void emitDirectiveNaNLegacy() override;
virtual void emitDirectiveOptionPic0(); void emitDirectiveOptionPic0() override;
virtual void emitDirectiveOptionPic2(); void emitDirectiveOptionPic2() override;
virtual void emitFrame(unsigned StackReg, unsigned StackSize, void emitFrame(unsigned StackReg, unsigned StackSize,
unsigned ReturnReg); unsigned ReturnReg) override;
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff); void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff); void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
virtual void emitDirectiveSetMips32R2(); void emitDirectiveSetMips32R2() override;
virtual void emitDirectiveSetMips64(); void emitDirectiveSetMips64() override;
virtual void emitDirectiveSetMips64R2(); void emitDirectiveSetMips64R2() override;
virtual void emitDirectiveSetDsp(); void emitDirectiveSetDsp() override;
}; };
} }
#endif #endif