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[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207506 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-04-29 07:58:02 +00:00
parent 6b7b725179
commit 91b10fb0e9
38 changed files with 390 additions and 392 deletions
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28
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -75,10 +75,10 @@ class MipsAsmParser : public MCTargetAsmParser {
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
SmallVectorImpl<MCParsedAsmOperand *> &Operands,
MCStreamer &Out, unsigned &ErrorInfo,
bool MatchingInlineAsm);
bool MatchingInlineAsm) override;
/// Parse a register as used in CFI directives
bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
bool ParseParenSuffix(StringRef Name,
SmallVectorImpl<MCParsedAsmOperand *> &Operands);
@ -86,11 +86,11 @@ class MipsAsmParser : public MCTargetAsmParser {
bool ParseBracketSuffix(StringRef Name,
SmallVectorImpl<MCParsedAsmOperand *> &Operands);
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand *> &Operands);
bool
ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand *> &Operands) override;
bool ParseDirective(AsmToken DirectiveID);
bool ParseDirective(AsmToken DirectiveID) override;
MipsAsmParser::OperandMatchResultTy
parseMemOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
@ -577,7 +577,7 @@ public:
addExpr(Inst, Expr);
}
bool isReg() const {
bool isReg() const override {
// As a special case until we sort out the definition of div/divu, pretend
// that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
if (isGPRAsmReg() && RegIdx.Index == 0)
@ -586,16 +586,16 @@ public:
return Kind == k_PhysRegister;
}
bool isRegIdx() const { return Kind == k_RegisterIndex; }
bool isImm() const { return Kind == k_Immediate; }
bool isImm() const override { return Kind == k_Immediate; }
bool isConstantImm() const {
return isImm() && dyn_cast<MCConstantExpr>(getImm());
}
bool isToken() const {
bool isToken() const override {
// Note: It's not possible to pretend that other operand kinds are tokens.
// The matcher emitter checks tokens first.
return Kind == k_Token;
}
bool isMem() const { return Kind == k_Memory; }
bool isMem() const override { return Kind == k_Memory; }
bool isInvNum() const { return Kind == k_Immediate; }
bool isLSAImm() const {
if (!isConstantImm())
@ -609,7 +609,7 @@ public:
return StringRef(Tok.Data, Tok.Length);
}
unsigned getReg() const {
unsigned getReg() const override {
// As a special case until we sort out the definition of div/divu, pretend
// that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
@ -756,9 +756,9 @@ public:
}
/// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const { return StartLoc; }
SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Get the location of the last token of this operand.
SMLoc getEndLoc() const { return EndLoc; }
SMLoc getEndLoc() const override { return EndLoc; }
virtual ~MipsOperand() {
switch (Kind) {
@ -774,7 +774,7 @@ public:
}
}
virtual void print(raw_ostream &OS) const {
void print(raw_ostream &OS) const override {
switch (Kind) {
case k_Immediate:
OS << "Imm<";

8
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -64,12 +64,12 @@ public:
}
/// getInstruction - See MCDisassembler.
virtual DecodeStatus getInstruction(MCInst &instr,
DecodeStatus getInstruction(MCInst &instr,
uint64_t &size,
const MemoryObject &region,
uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const;
raw_ostream &cStream) const override;
};
@ -83,12 +83,12 @@ public:
MipsDisassemblerBase(STI, Ctx, bigEndian) {}
/// getInstruction - See MCDisassembler.
virtual DecodeStatus getInstruction(MCInst &instr,
DecodeStatus getInstruction(MCInst &instr,
uint64_t &size,
const MemoryObject &region,
uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const;
raw_ostream &cStream) const override;
};
} // end anonymous namespace

4
lib/Target/Mips/InstPrinter/MipsInstPrinter.h
View File

@ -85,8 +85,8 @@ public:
void printInstruction(const MCInst *MI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
bool printAliasInstr(const MCInst *MI, raw_ostream &OS);

18
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
View File

@ -37,14 +37,14 @@ public:
: MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle),
Is64Bit(_is64Bit) {}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const;
MCObjectWriter *createObjectWriter(raw_ostream &OS) const override;
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value, bool IsPCRel) const;
uint64_t Value, bool IsPCRel) const override;
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
unsigned getNumFixupKinds() const {
unsigned getNumFixupKinds() const override {
return Mips::NumTargetFixupKinds;
}
@ -55,7 +55,7 @@ public:
/// relaxation.
///
/// \param Inst - The instruction to test.
bool mayNeedRelaxation(const MCInst &Inst) const {
bool mayNeedRelaxation(const MCInst &Inst) const override {
return false;
}
@ -63,7 +63,7 @@ public:
/// fixup requires the associated instruction to be relaxed.
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const {
const MCAsmLayout &Layout) const override {
// FIXME.
assert(0 && "RelaxInstruction() unimplemented");
return false;
@ -75,16 +75,16 @@ public:
/// \param Inst - The instruction to relax, which may be the same
/// as the output.
/// \param [out] Res On return, the relaxed instruction.
void relaxInstruction(const MCInst &Inst, MCInst &Res) const {}
void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {}
/// @}
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
const MCFixup &Fixup, const MCFragment *DF,
const MCValue &Target, uint64_t &Value,
bool &IsResolved);
bool &IsResolved) override;
}; // class MipsAsmBackend

2
lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
View File

@ -20,7 +20,7 @@ namespace llvm {
class StringRef;
class MipsMCAsmInfo : public MCAsmInfoELF {
virtual void anchor();
void anchor() override;
public:
explicit MipsMCAsmInfo(StringRef TT);
};

2
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
View File

@ -52,7 +52,7 @@ public:
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
const MCSubtargetInfo &STI) const override;
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.

10
lib/Target/Mips/MCTargetDesc/MipsMCExpr.h
View File

@ -46,16 +46,16 @@ public:
/// getSubExpr - Get the child of this expression.
const MCExpr *getSubExpr() const { return Expr; }
void PrintImpl(raw_ostream &OS) const;
void PrintImpl(raw_ostream &OS) const override;
bool EvaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout) const;
void AddValueSymbols(MCAssembler *) const;
const MCSection *FindAssociatedSection() const {
const MCAsmLayout *Layout) const override;
void AddValueSymbols(MCAssembler *) const override;
const MCSection *FindAssociatedSection() const override {
return getSubExpr()->FindAssociatedSection();
}
// There are no TLS MipsMCExprs at the moment.
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {}
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Target;

3
lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
View File

@ -120,7 +120,8 @@ private:
public:
/// This function is the one used to emit instruction data into the ELF
/// streamer. We override it to mask dangerous instructions.
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) {
void EmitInstruction(const MCInst &Inst,
const MCSubtargetInfo &STI) override {
// Sandbox indirect jumps.
if (isIndirectJump(Inst)) {
if (PendingCall)

14
lib/Target/Mips/Mips16FrameLowering.h
View File

@ -24,27 +24,27 @@ public:
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
void emitPrologue(MachineFunction &MF) const;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
MachineBasicBlock::iterator I) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;
bool hasReservedCallFrame(const MachineFunction &MF) const;
bool hasReservedCallFrame(const MachineFunction &MF) const override;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const;
RegScavenger *RS) const override;
};
} // End llvm namespace

4
lib/Target/Mips/Mips16HardFloat.h
View File

@ -34,11 +34,11 @@ public:
TM(TM_), Subtarget(TM.getSubtarget<MipsSubtarget>()) {
}
virtual const char *getPassName() const {
const char *getPassName() const override {
return "MIPS16 Hard Float Pass";
}
virtual bool runOnModule(Module &M);
bool runOnModule(Module &M) override;
protected:
/// Keep a pointer to the MipsSubtarget around so that we can make the right

10
lib/Target/Mips/Mips16ISelDAGToDAG.h
View File

@ -28,16 +28,16 @@ private:
SDValue getMips16SPAliasReg();
virtual bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
void getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg);
virtual bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
SDValue &Offset, SDValue &Alias);
bool selectAddr16(SDNode *Parent, SDValue N, SDValue &Base,
SDValue &Offset, SDValue &Alias) override;
virtual std::pair<bool, SDNode*> selectNode(SDNode *Node);
std::pair<bool, SDNode*> selectNode(SDNode *Node) override;
virtual void processFunctionAfterISel(MachineFunction &MF);
void processFunctionAfterISel(MachineFunction &MF) override;
// Insert instructions to initialize the global base register in the
// first MBB of the function.

19
lib/Target/Mips/Mips16ISelLowering.h
View File

@ -21,17 +21,17 @@ namespace llvm {
public:
explicit Mips16TargetLowering(MipsTargetMachine &TM);
virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
bool *Fast) const;
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
bool *Fast) const override;
virtual MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const override;
private:
virtual bool
isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
unsigned NextStackOffset,
const MipsFunctionInfo& FI) const;
const MipsFunctionInfo& FI) const override;
void setMips16HardFloatLibCalls();
@ -41,11 +41,12 @@ namespace llvm {
const char *getMips16HelperFunction
(Type* RetTy, ArgListTy &Args, bool &needHelper) const;
virtual void
void
getOpndList(SmallVectorImpl<SDValue> &Ops,
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
CallLoweringInfo &CLI, SDValue Callee,
SDValue Chain) const override;
MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI,
MachineBasicBlock *BB) const;

30
lib/Target/Mips/Mips16InstrInfo.h
View File

@ -25,46 +25,46 @@ class Mips16InstrInfo : public MipsInstrInfo {
public:
explicit Mips16InstrInfo(MipsTargetMachine &TM);
virtual const MipsRegisterInfo &getRegisterInfo() const;
const MipsRegisterInfo &getRegisterInfo() const override;
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
/// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
virtual void copyPhysReg(MachineBasicBlock &MBB,
void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
bool KillSrc) const override;
virtual void storeRegToStack(MachineBasicBlock &MBB,
void storeRegToStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
int64_t Offset) const;
int64_t Offset) const override;
virtual void loadRegFromStack(MachineBasicBlock &MBB,
void loadRegFromStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
int64_t Offset) const;
int64_t Offset) const override;
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
unsigned getOppositeBranchOpc(unsigned Opc) const override;
// Adjust SP by FrameSize bytes. Save RA, S0, S1
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
@ -104,9 +104,9 @@ public:
(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
unsigned getInlineAsmLength(const char *Str,
const MCAsmInfo &MAI) const;
const MCAsmInfo &MAI) const override;
private:
virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
unsigned getAnalyzableBrOpc(unsigned Opc) const override;
void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned Opc) const;

14
lib/Target/Mips/Mips16RegisterInfo.h
View File

@ -23,24 +23,24 @@ class Mips16RegisterInfo : public MipsRegisterInfo {
public:
Mips16RegisterInfo(const MipsSubtarget &Subtarget);
bool requiresRegisterScavenging(const MachineFunction &MF) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
bool useFPForScavengingIndex(const MachineFunction &MF) const;
bool useFPForScavengingIndex(const MachineFunction &MF) const override;
bool saveScavengerRegister(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
MachineBasicBlock::iterator &UseMI,
const TargetRegisterClass *RC,
unsigned Reg) const;
unsigned Reg) const override;
virtual const TargetRegisterClass *intRegClass(unsigned Size) const;
const TargetRegisterClass *intRegClass(unsigned Size) const override;
private:
virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
int FrameIndex, uint64_t StackSize,
int64_t SPOffset) const;
int64_t SPOffset) const override;
};
} // end namespace llvm

26
lib/Target/Mips/MipsAsmPrinter.h
View File

@ -87,13 +87,13 @@ public:
Subtarget = &TM.getSubtarget<MipsSubtarget>();
}
virtual const char *getPassName() const {
const char *getPassName() const override {
return "Mips Assembly Printer";
}
virtual bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
virtual void EmitConstantPool() override {
void EmitConstantPool() override {
bool UsingConstantPools =
(Subtarget->inMips16Mode() && Subtarget->useConstantIslands());
if (!UsingConstantPools)
@ -101,21 +101,21 @@ public:
// we emit constant pools customly!
}
void EmitInstruction(const MachineInstr *MI);
void EmitInstruction(const MachineInstr *MI) override;
void printSavedRegsBitmask();
void emitFrameDirective();
const char *getCurrentABIString() const;
virtual void EmitFunctionEntryLabel();
virtual void EmitFunctionBodyStart();
virtual void EmitFunctionBodyEnd();
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
MBB) const;
void EmitFunctionEntryLabel() override;
void EmitFunctionBodyStart() override;
void EmitFunctionBodyEnd() override;
bool isBlockOnlyReachableByFallthrough(
const MachineBasicBlock* MBB) const override;
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O);
raw_ostream &O) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O);
raw_ostream &O) override;
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
void printUnsignedImm8(const MachineInstr *MI, int opNum, raw_ostream &O);
@ -123,8 +123,8 @@ public:
void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O);
void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
const char *Modifier = nullptr);
void EmitStartOfAsmFile(Module &M);
void EmitEndOfAsmFile(Module &M);
void EmitStartOfAsmFile(Module &M) override;
void EmitEndOfAsmFile(Module &M) override;
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
};
}

6
lib/Target/Mips/MipsCodeEmitter.cpp
View File

@ -57,7 +57,7 @@ class MipsCodeEmitter : public MachineFunctionPass {
const std::vector<MachineJumpTableEntry> *MJTEs;
bool IsPIC;
void getAnalysisUsage(AnalysisUsage &AU) const {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineModuleInfo> ();
MachineFunctionPass::getAnalysisUsage(AU);
}
@ -70,9 +70,9 @@ public:
TM(tm), MCE(mce), MCPEs(nullptr), MJTEs(nullptr),
IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "Mips Machine Code Emitter";
}

4
lib/Target/Mips/MipsConstantIslandPass.cpp
View File

@ -371,11 +371,11 @@ namespace {
STI(&TM.getSubtarget<MipsSubtarget>()), MF(nullptr), MCP(nullptr),
PrescannedForConstants(false){}
virtual const char *getPassName() const {
const char *getPassName() const override {
return "Mips Constant Islands";
}
bool runOnMachineFunction(MachineFunction &F);
bool runOnMachineFunction(MachineFunction &F) override;
void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);
CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);

12
lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -124,7 +124,7 @@ namespace {
public:
NoMemInstr() : InspectMemInstr(true) {}
private:
virtual bool hasHazard_(const MachineInstr &MI) { return true; }
bool hasHazard_(const MachineInstr &MI) override { return true; }
};
/// This subclass accepts loads from stacks and constant loads.
@ -132,7 +132,7 @@ namespace {
public:
LoadFromStackOrConst() : InspectMemInstr(false) {}
private:
virtual bool hasHazard_(const MachineInstr &MI);
bool hasHazard_(const MachineInstr &MI) override;
};
/// This subclass uses memory dependence information to determine whether a
@ -144,7 +144,7 @@ namespace {
private:
typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType;
virtual bool hasHazard_(const MachineInstr &MI);
bool hasHazard_(const MachineInstr &MI) override;
/// Update Defs and Uses. Return true if there exist dependences that
/// disqualify the delay slot candidate between V and values in Uses and
@ -168,11 +168,11 @@ namespace {
Filler(TargetMachine &tm)
: MachineFunctionPass(ID), TM(tm) { }
virtual const char *getPassName() const {
const char *getPassName() const override {
return "Mips Delay Slot Filler";
}
bool runOnMachineFunction(MachineFunction &F) {
bool runOnMachineFunction(MachineFunction &F) override {
bool Changed = false;
for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI)
@ -180,7 +180,7 @@ namespace {
return Changed;
}
void getAnalysisUsage(AnalysisUsage &AU) const {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineBranchProbabilityInfo>();
MachineFunctionPass::getAnalysisUsage(AU);
}

2
lib/Target/Mips/MipsFrameLowering.h
View File

@ -32,7 +32,7 @@ public:
static const MipsFrameLowering *create(MipsTargetMachine &TM,
const MipsSubtarget &ST);
bool hasFP(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const override;
protected:
uint64_t estimateStackSize(const MachineFunction &MF) const;

10
lib/Target/Mips/MipsISelDAGToDAG.h
View File

@ -35,11 +35,11 @@ public:
: SelectionDAGISel(TM), Subtarget(TM.getSubtarget<MipsSubtarget>()) {}
// Pass Name
virtual const char *getPassName() const {
const char *getPassName() const override {
return "MIPS DAG->DAG Pattern Instruction Selection";
}
virtual bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
protected:
SDNode *getGlobalBaseReg();
@ -110,7 +110,7 @@ private:
/// starting at bit zero.
virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const;
virtual SDNode *Select(SDNode *N);
SDNode *Select(SDNode *N) override;
virtual std::pair<bool, SDNode*> selectNode(SDNode *Node) = 0;
@ -121,9 +121,9 @@ private:
virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDValue> &OutOps);
std::vector<SDValue> &OutOps) override;
};
/// createMipsISelDag - This pass converts a legalized DAG into a

65
lib/Target/Mips/MipsISelLowering.h
View File

@ -223,32 +223,33 @@ namespace llvm {
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo) const override;
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
virtual void LowerOperationWrapper(SDNode *N,
void LowerOperationWrapper(SDNode *N,
SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const;
SelectionDAG &DAG) const override;
/// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
/// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code.
///
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const;
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const override;
/// getTargetNodeName - This method returns the name of a target specific
// DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;
const char *getTargetNodeName(unsigned Opcode) const override;
/// getSetCCResultType - get the ISD::SETCC result ValueType
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
virtual MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const override;
struct LTStr {
bool operator()(const char *S1, const char *S2) const {
@ -528,41 +529,39 @@ namespace llvm {
void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
SDValue Chain, SDLoc DL, SelectionDAG &DAG) const;
virtual SDValue
SDValue
LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
SmallVectorImpl<SDValue> &InVals) const override;
SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
SDValue Arg, SDLoc DL, bool IsTailCall,
SelectionDAG &DAG) const;
virtual SDValue
LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const override;
virtual bool
CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const;
LLVMContext &Context) const override;
virtual SDValue
LowerReturn(SDValue Chain,
SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
SDLoc dl, SelectionDAG &DAG) const;
SDLoc dl, SelectionDAG &DAG) const override;
// Inline asm support
ConstraintType getConstraintType(const std::string &Constraint) const;
ConstraintType
getConstraintType(const std::string &Constraint) const override;
/// Examine constraint string and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type.
ConstraintWeight getSingleConstraintMatchWeight(
AsmOperandInfo &info, const char *constraint) const;
AsmOperandInfo &info, const char *constraint) const override;
/// This function parses registers that appear in inline-asm constraints.
/// It returns pair (0, 0) on failure.
@ -571,33 +570,33 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const;
MVT VT) const override;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
/// true it means one of the asm constraint of the inline asm instruction
/// being processed is 'm'.
virtual void LowerAsmOperandForConstraint(SDValue Op,
void LowerAsmOperandForConstraint(SDValue Op,
std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
SelectionDAG &DAG) const override;
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
unsigned SrcAlign,
bool IsMemset, bool ZeroMemset,
bool MemcpyStrSrc,
MachineFunction &MF) const;
MachineFunction &MF) const override;
/// isFPImmLegal - Returns true if the target can instruction select the
/// specified FP immediate natively. If false, the legalizer will
/// materialize the FP immediate as a load from a constant pool.
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
virtual unsigned getJumpTableEncoding() const;
unsigned getJumpTableEncoding() const override;
MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
unsigned Size, unsigned BinOpcode, bool Nand = false) const;

26
lib/Target/Mips/MipsInstrInfo.h
View File

@ -47,20 +47,20 @@ public:
static const MipsInstrInfo *create(MipsTargetMachine &TM);
/// Branch Analysis
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const;
bool AllowModify) const override;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
DebugLoc DL) const override;
virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
@ -69,8 +69,8 @@ public:
SmallVectorImpl<MachineInstr*> &BranchInstrs) const;
/// Insert nop instruction when hazard condition is found
virtual void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const;
void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override;
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
@ -83,19 +83,19 @@ public:
/// Return the number of bytes of code the specified instruction may be.
unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
const TargetRegisterInfo *TRI) const override {
storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
}
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
const TargetRegisterInfo *TRI) const override {
loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
}

14
lib/Target/Mips/MipsJITInfo.h
View File

@ -37,26 +37,26 @@ class MipsJITInfo : public TargetJITInfo {
/// overwriting OLD with a branch to NEW. This is used for self-modifying
/// code.
///
virtual void replaceMachineCodeForFunction(void *Old, void *New);
void replaceMachineCodeForFunction(void *Old, void *New) override;
// getStubLayout - Returns the size and alignment of the largest call stub
// on Mips.
virtual StubLayout getStubLayout();
StubLayout getStubLayout() override;
/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
/// small native function that simply calls the function at the specified
/// address.
virtual void *emitFunctionStub(const Function *F, void *Fn,
JITCodeEmitter &JCE);
void *emitFunctionStub(const Function *F, void *Fn,
JITCodeEmitter &JCE) override;
/// getLazyResolverFunction - Expose the lazy resolver to the JIT.
virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
/// relocate - Before the JIT can run a block of code that has been emitted,
/// it must rewrite the code to contain the actual addresses of any
/// referenced global symbols.
virtual void relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char *GOTBase);
void relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char *GOTBase) override;
/// Initialize - Initialize internal stage for the function being JITted.
void Initialize(const MachineFunction &MF, bool isPIC,

4
lib/Target/Mips/MipsLongBranch.cpp
View File

@ -69,11 +69,11 @@ namespace {
ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()),
LongBranchSeqSize(!IsPIC ? 2 : (ABI == MipsSubtarget::N64 ? 13 : 9)) {}
virtual const char *getPassName() const {
const char *getPassName() const override {
return "Mips Long Branch";
}
bool runOnMachineFunction(MachineFunction &F);
bool runOnMachineFunction(MachineFunction &F) override;
private:
void splitMBB(MachineBasicBlock *MBB);

8
lib/Target/Mips/MipsMachineFunction.h
View File

@ -37,12 +37,12 @@ class MipsCallEntry : public PseudoSourceValue {
public:
explicit MipsCallEntry(const StringRef &N);
explicit MipsCallEntry(const GlobalValue *V);
virtual bool isConstant(const MachineFrameInfo *) const;
virtual bool isAliased(const MachineFrameInfo *) const;
virtual bool mayAlias(const MachineFrameInfo *) const;
bool isConstant(const MachineFrameInfo *) const override;
bool isAliased(const MachineFrameInfo *) const override;
bool mayAlias(const MachineFrameInfo *) const override;
private:
virtual void printCustom(raw_ostream &O) const;
void printCustom(raw_ostream &O) const override;
#ifndef NDEBUG
std::string Name;
const GlobalValue *Val;

8
lib/Target/Mips/MipsModuleISelDAGToDAG.h
View File

@ -41,15 +41,11 @@ public:
TM(TM_), Subtarget(TM.getSubtarget<MipsSubtarget>()) {}
// Pass Name
virtual const char *getPassName() const {
const char *getPassName() const override {
return "MIPS DAG->DAG Pattern Instruction Selection";
}
virtual bool runOnMachineFunction(MachineFunction &MF);
virtual SDNode *Select(SDNode *N) {
llvm_unreachable("unexpected");
}
bool runOnMachineFunction(MachineFunction &MF) override;
protected:
/// Keep a pointer to the MipsSubtarget around so that we can make the right

6
lib/Target/Mips/MipsOptimizePICCall.cpp
View File

@ -61,11 +61,11 @@ class OptimizePICCall : public MachineFunctionPass {
public:
OptimizePICCall(TargetMachine &tm) : MachineFunctionPass(ID) {}
virtual const char *getPassName() const { return "Mips OptimizePICCall"; }
const char *getPassName() const override { return "Mips OptimizePICCall"; }
bool runOnMachineFunction(MachineFunction &F);
bool runOnMachineFunction(MachineFunction &F) override;
void getAnalysisUsage(AnalysisUsage &AU) const {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineDominatorTree>();
MachineFunctionPass::getAnalysisUsage(AU);
}

4
lib/Target/Mips/MipsOs16.h
View File

@ -34,11 +34,11 @@ public:
}
virtual const char *getPassName() const {
const char *getPassName() const override {
return "MIPS Os16 Optimization";
}
virtual bool runOnModule(Module &M);
bool runOnModule(Module &M) override;
};

19
lib/Target/Mips/MipsRegisterInfo.h
View File

@ -43,30 +43,31 @@ public:
/// Code Generation virtual methods...
const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
unsigned Kind) const;
unsigned Kind) const override;
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
const uint32_t *getCallPreservedMask(CallingConv::ID) const;
MachineFunction &MF) const override;
const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
static const uint32_t *getMips16RetHelperMask();
BitVector getReservedRegs(const MachineFunction &MF) const;
BitVector getReservedRegs(const MachineFunction &MF) const override;
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
/// Stack Frame Processing Methods
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const;
RegScavenger *RS = nullptr) const override;
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = nullptr) const;
/// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const;
unsigned getFrameRegister(const MachineFunction &MF) const override;
/// \brief Return GPR register class.
virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;

12
lib/Target/Mips/MipsSEFrameLowering.h
View File

@ -25,22 +25,22 @@ public:
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
void emitPrologue(MachineFunction &MF) const;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
MachineBasicBlock::iterator I) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;
bool hasReservedCallFrame(const MachineFunction &MF) const;
bool hasReservedCallFrame(const MachineFunction &MF) const override;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const;
RegScavenger *RS) const override;
unsigned ehDataReg(unsigned I) const;
};

70
lib/Target/Mips/MipsSEISelDAGToDAG.h
View File

@ -25,7 +25,7 @@ public:
private:
virtual bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
MachineFunction &MF);
@ -44,66 +44,66 @@ private:
bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
unsigned OffsetBits) const;
virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
bool selectAddrRegImm(SDValue Addr, SDValue &Base,
SDValue &Offset) const override;
bool selectAddrRegReg(SDValue Addr, SDValue &Base,
SDValue &Offset) const override;
bool selectAddrDefault(SDValue Addr, SDValue &Base,
SDValue &Offset) const override;
bool selectIntAddr(SDValue Addr, SDValue &Base,
SDValue &Offset) const override;
bool selectAddrRegImm10(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base,
bool selectAddrRegImm12(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
bool selectIntAddrMM(SDValue Addr, SDValue &Base,
SDValue &Offset) const override;
virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
virtual bool selectAddrRegImm10(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
virtual bool selectAddrRegImm12(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
SDValue &Offset) const;
bool selectIntAddrMSA(SDValue Addr, SDValue &Base,
SDValue &Offset) const override;
/// \brief Select constant vector splats.
virtual bool selectVSplat(SDNode *N, APInt &Imm) const;
bool selectVSplat(SDNode *N, APInt &Imm) const override;
/// \brief Select constant vector splats whose value fits in a given integer.
virtual bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
unsigned ImmBitSize) const;
/// \brief Select constant vector splats whose value fits in a uimm1.
virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm2.
virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm3.
virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm4.
virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm5.
virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm6.
virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a uimm8.
virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value fits in a simm5.
virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value is a power of 2.
virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value is the inverse of a
/// power of 2.
virtual bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const;
bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value is a run of set bits
/// ending at the most significant bit
virtual bool selectVSplatMaskL(SDValue N, SDValue &Imm) const;
bool selectVSplatMaskL(SDValue N, SDValue &Imm) const override;
/// \brief Select constant vector splats whose value is a run of set bits
/// starting at bit zero.
virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const;
bool selectVSplatMaskR(SDValue N, SDValue &Imm) const override;
virtual std::pair<bool, SDNode*> selectNode(SDNode *Node);
std::pair<bool, SDNode*> selectNode(SDNode *Node) override;
virtual void processFunctionAfterISel(MachineFunction &MF);
void processFunctionAfterISel(MachineFunction &MF) override;
// Insert instructions to initialize the global base register in the
// first MBB of the function.

25
lib/Target/Mips/MipsSEISelLowering.h
View File

@ -33,19 +33,20 @@ namespace llvm {
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0,
bool *Fast = nullptr) const override;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
virtual MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const override;
virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
EVT VT) const {
bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
EVT VT) const override {
return false;
}
virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
const TargetRegisterClass *getRepRegClassFor(MVT VT) const override {
if (VT == MVT::Untyped)
return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
&Mips::ACC64RegClass;
@ -54,16 +55,16 @@ namespace llvm {
}
private:
virtual bool
isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
unsigned NextStackOffset,
const MipsFunctionInfo& FI) const;
const MipsFunctionInfo& FI) const override;
virtual void
void
getOpndList(SmallVectorImpl<SDValue> &Ops,
std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
CallLoweringInfo &CLI, SDValue Callee,
SDValue Chain) const override;
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;

28
lib/Target/Mips/MipsSEInstrInfo.h
View File

@ -26,46 +26,46 @@ class MipsSEInstrInfo : public MipsInstrInfo {
public:
explicit MipsSEInstrInfo(MipsTargetMachine &TM);
virtual const MipsRegisterInfo &getRegisterInfo() const;
const MipsRegisterInfo &getRegisterInfo() const override;
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
/// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
virtual void copyPhysReg(MachineBasicBlock &MBB,
void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
bool KillSrc) const override;
virtual void storeRegToStack(MachineBasicBlock &MBB,
void storeRegToStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
int64_t Offset) const;
int64_t Offset) const override;
virtual void loadRegFromStack(MachineBasicBlock &MBB,
void loadRegFromStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
int64_t Offset) const;
int64_t Offset) const override;
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
unsigned getOppositeBranchOpc(unsigned Opc) const override;
/// Adjust SP by Amount bytes.
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
@ -79,7 +79,7 @@ public:
unsigned *NewImm) const;
private:
virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
unsigned getAnalyzableBrOpc(unsigned Opc) const override;
void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned Opc) const;

10
lib/Target/Mips/MipsSERegisterInfo.h
View File

@ -24,16 +24,16 @@ class MipsSERegisterInfo : public MipsRegisterInfo {
public:
MipsSERegisterInfo(const MipsSubtarget &Subtarget);
bool requiresRegisterScavenging(const MachineFunction &MF) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
virtual const TargetRegisterClass *intRegClass(unsigned Size) const;
const TargetRegisterClass *intRegClass(unsigned Size) const override;
private:
virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
int FrameIndex, uint64_t StackSize,
int64_t SPOffset) const;
int64_t SPOffset) const override;
};
} // end namespace llvm

4
lib/Target/Mips/MipsSubtarget.h
View File

@ -130,9 +130,9 @@ protected:
Triple TargetTriple;
public:
virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const;
RegClassVector& CriticalPathRCs) const override;
/// Only O32 and EABI supported right now.
bool isABI_EABI() const { return MipsABI == EABI; }

10
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -171,12 +171,12 @@ public:
return *getMipsTargetMachine().getSubtargetImpl();
}
virtual void addIRPasses();
virtual bool addInstSelector();
virtual void addMachineSSAOptimization();
virtual bool addPreEmitPass();
void addIRPasses() override;
bool addInstSelector() override;
void addMachineSSAOptimization() override;
bool addPreEmitPass() override;
virtual bool addPreRegAlloc();
bool addPreRegAlloc() override;
};
} // namespace

25
lib/Target/Mips/MipsTargetMachine.h
View File

@ -55,39 +55,38 @@ public:
virtual ~MipsTargetMachine() {}
virtual void addAnalysisPasses(PassManagerBase &PM);
void addAnalysisPasses(PassManagerBase &PM) override;
virtual const MipsInstrInfo *getInstrInfo() const
const MipsInstrInfo *getInstrInfo() const override
{ return InstrInfo.get(); }
virtual const TargetFrameLowering *getFrameLowering() const
const TargetFrameLowering *getFrameLowering() const override
{ return FrameLowering.get(); }
virtual const MipsSubtarget *getSubtargetImpl() const
const MipsSubtarget *getSubtargetImpl() const override
{ return &Subtarget; }
virtual const DataLayout *getDataLayout() const
const DataLayout *getDataLayout() const override
{ return &DL;}
virtual const InstrItineraryData *getInstrItineraryData() const {
const InstrItineraryData *getInstrItineraryData() const override {
return Subtarget.inMips16Mode() ? nullptr : &InstrItins;
}
virtual MipsJITInfo *getJITInfo()
{ return &JITInfo; }
MipsJITInfo *getJITInfo() override { return &JITInfo; }
virtual const MipsRegisterInfo *getRegisterInfo() const {
const MipsRegisterInfo *getRegisterInfo() const override {
return &InstrInfo->getRegisterInfo();
}
virtual const MipsTargetLowering *getTargetLowering() const {
const MipsTargetLowering *getTargetLowering() const override {
return TLInfo.get();
}
virtual const MipsSelectionDAGInfo* getSelectionDAGInfo() const {
const MipsSelectionDAGInfo* getSelectionDAGInfo() const override {
return &TSInfo;
}
// Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
// Set helper classes
void setHelperClassesMips16();

104
lib/Target/Mips/MipsTargetStreamer.h
View File

@ -55,34 +55,34 @@ class MipsTargetAsmStreamer : public MipsTargetStreamer {
public:
MipsTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
virtual void emitDirectiveSetMicroMips();
virtual void emitDirectiveSetNoMicroMips();
virtual void emitDirectiveSetMips16();
virtual void emitDirectiveSetNoMips16();
void emitDirectiveSetMicroMips() override;
void emitDirectiveSetNoMicroMips() override;
void emitDirectiveSetMips16() override;
void emitDirectiveSetNoMips16() override;
virtual void emitDirectiveSetReorder();
virtual void emitDirectiveSetNoReorder();
virtual void emitDirectiveSetMacro();
virtual void emitDirectiveSetNoMacro();
virtual void emitDirectiveSetAt();
virtual void emitDirectiveSetNoAt();
virtual void emitDirectiveEnd(StringRef Name);
void emitDirectiveSetReorder() override;
void emitDirectiveSetNoReorder() override;
void emitDirectiveSetMacro() override;
void emitDirectiveSetNoMacro() override;
void emitDirectiveSetAt() override;
void emitDirectiveSetNoAt() override;
void emitDirectiveEnd(StringRef Name) override;
virtual void emitDirectiveEnt(const MCSymbol &Symbol);
virtual void emitDirectiveAbiCalls();
virtual void emitDirectiveNaN2008();
virtual void emitDirectiveNaNLegacy();
virtual void emitDirectiveOptionPic0();
virtual void emitDirectiveOptionPic2();
virtual void emitFrame(unsigned StackReg, unsigned StackSize,
unsigned ReturnReg);
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff);
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff);
void emitDirectiveEnt(const MCSymbol &Symbol) override;
void emitDirectiveAbiCalls() override;
void emitDirectiveNaN2008() override;
void emitDirectiveNaNLegacy() override;
void emitDirectiveOptionPic0() override;
void emitDirectiveOptionPic2() override;
void emitFrame(unsigned StackReg, unsigned StackSize,
unsigned ReturnReg) override;
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
virtual void emitDirectiveSetMips32R2();
virtual void emitDirectiveSetMips64();
virtual void emitDirectiveSetMips64R2();
virtual void emitDirectiveSetDsp();
void emitDirectiveSetMips32R2() override;
void emitDirectiveSetMips64() override;
void emitDirectiveSetMips64R2() override;
void emitDirectiveSetDsp() override;
};
// This part is for ELF object output
@ -96,38 +96,38 @@ public:
MCELFStreamer &getStreamer();
MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
virtual void emitLabel(MCSymbol *Symbol) override;
virtual void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override;
void emitLabel(MCSymbol *Symbol) override;
void emitAssignment(MCSymbol *Symbol, const MCExpr *Value) override;
void finish() override;
virtual void emitDirectiveSetMicroMips();
virtual void emitDirectiveSetNoMicroMips();
virtual void emitDirectiveSetMips16();
virtual void emitDirectiveSetNoMips16();
void emitDirectiveSetMicroMips() override;
void emitDirectiveSetNoMicroMips() override;
void emitDirectiveSetMips16() override;
void emitDirectiveSetNoMips16() override;
virtual void emitDirectiveSetReorder();
virtual void emitDirectiveSetNoReorder();
virtual void emitDirectiveSetMacro();
virtual void emitDirectiveSetNoMacro();
virtual void emitDirectiveSetAt();
virtual void emitDirectiveSetNoAt();
virtual void emitDirectiveEnd(StringRef Name);
void emitDirectiveSetReorder() override;
void emitDirectiveSetNoReorder() override;
void emitDirectiveSetMacro() override;
void emitDirectiveSetNoMacro() override;
void emitDirectiveSetAt() override;
void emitDirectiveSetNoAt() override;
void emitDirectiveEnd(StringRef Name) override;
virtual void emitDirectiveEnt(const MCSymbol &Symbol);
virtual void emitDirectiveAbiCalls();
virtual void emitDirectiveNaN2008();
virtual void emitDirectiveNaNLegacy();
virtual void emitDirectiveOptionPic0();
virtual void emitDirectiveOptionPic2();
virtual void emitFrame(unsigned StackReg, unsigned StackSize,
unsigned ReturnReg);
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff);
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff);
void emitDirectiveEnt(const MCSymbol &Symbol) override;
void emitDirectiveAbiCalls() override;
void emitDirectiveNaN2008() override;
void emitDirectiveNaNLegacy() override;
void emitDirectiveOptionPic0() override;
void emitDirectiveOptionPic2() override;
void emitFrame(unsigned StackReg, unsigned StackSize,
unsigned ReturnReg) override;
void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override;
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
virtual void emitDirectiveSetMips32R2();
virtual void emitDirectiveSetMips64();
virtual void emitDirectiveSetMips64R2();
virtual void emitDirectiveSetDsp();
void emitDirectiveSetMips32R2() override;
void emitDirectiveSetMips64() override;
void emitDirectiveSetMips64R2() override;
void emitDirectiveSetDsp() override;
};
}
#endif