mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
Promote v4i32, v8i16, v16i8 load to v2i64 load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27612 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
c010c13f36
commit
91b740da12
@ -302,10 +302,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SUB, MVT::v4i32, Legal);
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setOperationAction(ISD::MUL, MVT::v2f64, Legal);
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setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
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setOperationAction(ISD::LOAD, MVT::v16i8, Legal);
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setOperationAction(ISD::LOAD, MVT::v8i16, Legal);
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setOperationAction(ISD::LOAD, MVT::v4i32, Legal);
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setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
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@ -329,7 +325,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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VT != (unsigned)MVT::v2i64; VT++) {
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setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
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AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
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setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
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AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
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}
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setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
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setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
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setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
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}
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@ -531,7 +531,7 @@ def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
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def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
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"cvttsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvttsd2si
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(load addr:$src)))]>;
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(loadv2f64 addr:$src)))]>;
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def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"cvtsd2si {$src, $dst|$dst, $src}",
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@ -539,7 +539,7 @@ def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
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def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
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"cvtsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvtsd2si
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(load addr:$src)))]>;
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(loadv2f64 addr:$src)))]>;
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// Comparison instructions
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let isTwoAddress = 1 in {
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@ -834,7 +834,7 @@ def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
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"cvtdq2ps {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2ps
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(load addr:$src)))]>,
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(bc_v4i32 (loadv2i64 addr:$src))))]>,
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TB, Requires<[HasSSE2]>;
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// SSE2 instructions with XS prefix
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@ -845,7 +845,7 @@ def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtdq2pd {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtdq2pd
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(load addr:$src)))]>,
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(bc_v4i32 (loadv2i64 addr:$src))))]>,
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XS, Requires<[HasSSE2]>;
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def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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@ -863,7 +863,7 @@ def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"cvtps2dq {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq
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(load addr:$src)))]>;
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(loadv4f32 addr:$src)))]>;
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// SSE2 packed instructions with XS prefix
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def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"cvttps2dq {$src, $dst|$dst, $src}",
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@ -872,7 +872,7 @@ def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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def CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"cvttps2dq {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttps2dq
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(load addr:$src)))]>,
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(loadv4f32 addr:$src)))]>,
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XS, Requires<[HasSSE2]>;
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// SSE2 packed instructions with XD prefix
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@ -883,7 +883,7 @@ def CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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def CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"cvtpd2dq {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2dq
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(load addr:$src)))]>,
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(loadv2f64 addr:$src)))]>,
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XD, Requires<[HasSSE2]>;
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def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"cvttpd2dq {$src, $dst|$dst, $src}",
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@ -891,7 +891,7 @@ def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
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"cvttpd2dq {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvttpd2dq
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(load addr:$src)))]>;
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(loadv2f64 addr:$src)))]>;
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// SSE2 instructions without OpSize prefix
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def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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@ -901,7 +901,7 @@ def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
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"cvtps2pd {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2pd
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(load addr:$src)))]>,
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(loadv4f32 addr:$src)))]>,
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TB, Requires<[HasSSE2]>;
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def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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@ -910,7 +910,7 @@ def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
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"cvtpd2ps {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtpd2ps
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(load addr:$src)))]>;
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(loadv2f64 addr:$src)))]>;
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// Arithmetic
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let isTwoAddress = 1 in {
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@ -1226,10 +1226,10 @@ def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"movdqa {$src, $dst|$dst, $src}", []>;
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def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
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"movdqa {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (loadv4i32 addr:$src))]>;
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[(set VR128:$dst, (loadv2i64 addr:$src))]>;
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def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
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"movdqa {$src, $dst|$dst, $src}",
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[(store (v4i32 VR128:$src), addr:$dst)]>;
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[(store (v2i64 VR128:$src), addr:$dst)]>;
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// 128-bit Integer Arithmetic
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let isTwoAddress = 1 in {
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@ -1394,7 +1394,8 @@ def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
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(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
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"pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (v4i32 (vector_shuffle
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(load addr:$src1), (undef),
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(bc_v4i32 (loadv2i64 addr:$src1)),
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(undef),
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PSHUFD_shuffle_mask:$src2)))]>;
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// SSE2 with ImmT == Imm8 and XS prefix.
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@ -1409,7 +1410,8 @@ def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
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(ops VR128:$dst, i128mem:$src1, i8imm:$src2),
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"pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (v8i16 (vector_shuffle
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(load addr:$src1), (undef),
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(bc_v8i16 (loadv2i64 addr:$src1)),
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(undef),
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PSHUFHW_shuffle_mask:$src2)))]>,
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XS, Requires<[HasSSE2]>;
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@ -1425,7 +1427,8 @@ def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
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(ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
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"pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst, (v8i16 (vector_shuffle
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(load addr:$src1), (undef),
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(bc_v8i16 (loadv2i64 addr:$src1)),
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(undef),
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PSHUFLW_shuffle_mask:$src2)))]>,
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XD, Requires<[HasSSE2]>;
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@ -1440,7 +1443,8 @@ def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpcklbw {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v16i8 (vector_shuffle VR128:$src1, (load addr:$src2),
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(v16i8 (vector_shuffle VR128:$src1,
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(bc_v16i8 (loadv2i64 addr:$src2)),
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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@ -1452,7 +1456,8 @@ def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpcklwd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v8i16 (vector_shuffle VR128:$src1, (load addr:$src2),
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(v8i16 (vector_shuffle VR128:$src1,
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(bc_v8i16 (loadv2i64 addr:$src2)),
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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@ -1464,7 +1469,8 @@ def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpckldq {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
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(v4i32 (vector_shuffle VR128:$src1,
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(bc_v4i32 (loadv2i64 addr:$src2)),
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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@ -1476,7 +1482,8 @@ def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpcklqdq {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
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(v2i64 (vector_shuffle VR128:$src1,
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(loadv2i64 addr:$src2),
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UNPCKL_shuffle_mask)))]>;
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def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
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@ -1489,7 +1496,8 @@ def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpckhbw {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v16i8 (vector_shuffle VR128:$src1, (load addr:$src2),
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(v16i8 (vector_shuffle VR128:$src1,
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(bc_v16i8 (loadv2i64 addr:$src2)),
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UNPCKH_shuffle_mask)))]>;
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def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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@ -1501,7 +1509,8 @@ def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpckhwd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v8i16 (vector_shuffle VR128:$src1, (load addr:$src2),
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(v8i16 (vector_shuffle VR128:$src1,
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(bc_v8i16 (loadv2i64 addr:$src2)),
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UNPCKH_shuffle_mask)))]>;
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def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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@ -1513,7 +1522,8 @@ def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpckhdq {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
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(v4i32 (vector_shuffle VR128:$src1,
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(bc_v4i32 (loadv2i64 addr:$src2)),
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UNPCKH_shuffle_mask)))]>;
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def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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@ -1525,7 +1535,8 @@ def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i128mem:$src2),
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"punpckhqdq {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
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(v2i64 (vector_shuffle VR128:$src1,
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(loadv2i64 addr:$src2),
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UNPCKH_shuffle_mask)))]>;
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}
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@ -1538,7 +1549,8 @@ def PEXTRWr : PDIi8<0xC5, MRMSrcReg,
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def PEXTRWm : PDIi8<0xC5, MRMSrcMem,
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(ops R32:$dst, i128mem:$src1, i32i8imm:$src2),
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"pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set R32:$dst, (X86pextrw (loadv8i16 addr:$src1),
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[(set R32:$dst, (X86pextrw
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(bc_v8i16 (loadv2i64 addr:$src1)),
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(i32 imm:$src2)))]>;
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let isTwoAddress = 1 in {
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@ -1773,16 +1785,6 @@ def : Pat<(v4i32 immAllOnesV), (v4i32 (V_SETALLONES))>, Requires<[HasSSE2]>;
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def : Pat<(v2i64 immAllOnesV), (v2i64 (V_SETALLONES))>, Requires<[HasSSE2]>;
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def : Pat<(v4f32 immAllOnesV), (v4f32 (V_SETALLONES))>, Requires<[HasSSE1]>;
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// Load 128-bit integer vector values.
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def : Pat<(v16i8 (load addr:$src)), (MOVDQArm addr:$src)>,
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Requires<[HasSSE2]>;
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def : Pat<(v8i16 (load addr:$src)), (MOVDQArm addr:$src)>,
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Requires<[HasSSE2]>;
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def : Pat<(v4i32 (load addr:$src)), (MOVDQArm addr:$src)>,
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Requires<[HasSSE2]>;
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def : Pat<(v2i64 (load addr:$src)), (MOVDQArm addr:$src)>,
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Requires<[HasSSE2]>;
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// Store 128-bit integer vector values.
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def : Pat<(store (v16i8 VR128:$src), addr:$dst),
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(MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
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@ -1790,8 +1792,6 @@ def : Pat<(store (v8i16 VR128:$src), addr:$dst),
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(MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
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def : Pat<(store (v4i32 VR128:$src), addr:$dst),
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(MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
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def : Pat<(store (v2i64 VR128:$src), addr:$dst),
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(MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
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// Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
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// 16-bits matter.
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@ -1885,21 +1885,6 @@ def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
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(v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
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Requires<[HasSSE1]>;
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// Special pshuf* cases: folding (bit_convert (loadv2i64 addr)).
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def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src1)), (undef),
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PSHUFD_shuffle_mask:$src2)),
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(PSHUFDmi addr:$src1, PSHUFD_shuffle_mask:$src2)>,
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Requires<[HasSSE2]>;
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def : Pat<(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
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PSHUFHW_shuffle_mask:$src2)),
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(PSHUFHWmi addr:$src1, PSHUFHW_shuffle_mask:$src2)>,
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Requires<[HasSSE2]>;
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def : Pat<(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
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PSHUFLW_shuffle_mask:$src2)),
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(PSHUFLWmi addr:$src1, PSHUFHW_shuffle_mask:$src2)>,
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Requires<[HasSSE2]>;
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// Special unary SHUFPSrr case.
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// FIXME: when we want non two-address code, then we should use PSHUFD?
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def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
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@ -1916,8 +1901,8 @@ def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
|
||||
PSHUFD_binary_shuffle_mask:$sm),
|
||||
(v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
|
||||
PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
|
||||
def : Pat<(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2),
|
||||
PSHUFD_binary_shuffle_mask:$sm),
|
||||
def : Pat<(vector_shuffle (v4i32 VR128:$src1),
|
||||
(bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
|
||||
(v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
|
||||
PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user