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X86: replace SUB with CMP if possible

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This patch will optimize the following
        movq    %rdi, %rax
        subq    %rsi, %rax
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax
to
        cmpq    %rsi, %rdi
        cmovsq  %rsi, %rdi
        movq    %rdi, %rax

Perform this optimization if the actual result of SUB is not used.

rdar: 11540023


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157755 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Manman Ren
2012-05-31 17:20:29 +00:00
parent 5ddc04caf2
commit 91c5346d91
5 changed files with 61 additions and 0 deletions
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38
lib/Target/X86/X86InstrInfo.cpp
View File

@@ -2709,6 +2709,44 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
NewMIs.push_back(MIB);
}
bool X86InstrInfo::
OptimizeSubInstr(MachineInstr *SubInstr, const MachineRegisterInfo *MRI) const {
// If destination is a memory operand, do not perform this optimization.
if ((SubInstr->getOpcode() != X86::SUB64rr) &&
(SubInstr->getOpcode() != X86::SUB32rr) &&
(SubInstr->getOpcode() != X86::SUB16rr) &&
(SubInstr->getOpcode() != X86::SUB8rr) &&
(SubInstr->getOpcode() != X86::SUB64ri32) &&
(SubInstr->getOpcode() != X86::SUB64ri8) &&
(SubInstr->getOpcode() != X86::SUB32ri) &&
(SubInstr->getOpcode() != X86::SUB32ri8) &&
(SubInstr->getOpcode() != X86::SUB16ri) &&
(SubInstr->getOpcode() != X86::SUB16ri8) &&
(SubInstr->getOpcode() != X86::SUB8ri))
return false;
unsigned DestReg = SubInstr->getOperand(0).getReg();
if (MRI->use_begin(DestReg) != MRI->use_end())
return false;
// There is no use of the destination register, we can replace SUB with CMP.
switch (SubInstr->getOpcode()) {
default: break;
case X86::SUB64rr: SubInstr->setDesc(get(X86::CMP64rr)); break;
case X86::SUB32rr: SubInstr->setDesc(get(X86::CMP32rr)); break;
case X86::SUB16rr: SubInstr->setDesc(get(X86::CMP16rr)); break;
case X86::SUB8rr: SubInstr->setDesc(get(X86::CMP8rr)); break;
case X86::SUB64ri32: SubInstr->setDesc(get(X86::CMP64ri32)); break;
case X86::SUB64ri8: SubInstr->setDesc(get(X86::CMP64ri8)); break;
case X86::SUB32ri: SubInstr->setDesc(get(X86::CMP32ri)); break;
case X86::SUB32ri8: SubInstr->setDesc(get(X86::CMP32ri8)); break;
case X86::SUB16ri: SubInstr->setDesc(get(X86::CMP16ri)); break;
case X86::SUB16ri8: SubInstr->setDesc(get(X86::CMP16ri8)); break;
case X86::SUB8ri: SubInstr->setDesc(get(X86::CMP8ri)); break;
}
SubInstr->RemoveOperand(0);
return true;
}
/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
/// instruction with two undef reads of the register being defined. This is
/// used for mapping:

3
lib/Target/X86/X86InstrInfo.h
View File

@@ -365,6 +365,9 @@ public:
const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI, unsigned UseIdx) const;
virtual bool OptimizeSubInstr(MachineInstr *SubInstr,
const MachineRegisterInfo *MRI) const;
private:
MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
MachineFunction::iterator &MFI,