From 91c655736e8a48ac4c464a1c95f29d6147370e57 Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Mon, 21 Apr 2014 21:45:57 +0000
Subject: [PATCH] ARM64: Improve diagnostics for malformed reg+reg addressing
 mode.

Make sure only general purpose registers are valid for offset regs and
that 32-bit regs are only valid for sxtw and uxtw extends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206799 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | 13 ++++++++++++-
 test/MC/ARM64/diags.s                         | 12 ++++++++++++
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index 24ed77a020f..4648f5cb0f8 100644
--- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -1416,7 +1416,7 @@ public:
     assert(N == 3 && "Invalid number of operands!");
 
     Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
-    Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
+    Inst.addOperand(MCOperand::CreateReg(getXRegFromWReg(Mem.OffsetRegNum)));
     unsigned ExtendImm = ARM64_AM::getMemExtendImm(Mem.ExtType, DoShift);
     Inst.addOperand(MCOperand::CreateImm(ExtendImm));
   }
@@ -2894,6 +2894,17 @@ bool ARM64AsmParser::parseMemory(OperandVector &Operands) {
 
         Parser.Lex(); // Eat the extend op.
 
+        // A 32-bit offset register is only valid for [SU]/XTW extend
+        // operators.
+        if (isGPR32Register(Reg2)) {
+         if (ExtOp != ARM64_AM::UXTW &&
+            ExtOp != ARM64_AM::SXTW)
+          return Error(ExtLoc, "32-bit general purpose offset register "
+                               "requires sxtw or uxtw extend");
+        } else if (!isGPR64Register(Reg2))
+          return Error(OffsetLoc,
+                       "64-bit general purpose offset register expected");
+
         bool Hash = getLexer().is(AsmToken::Hash);
         if (getLexer().is(AsmToken::RBrac)) {
           // No immediate operand.
diff --git a/test/MC/ARM64/diags.s b/test/MC/ARM64/diags.s
index e82147e6c2b..424d9547fe8 100644
--- a/test/MC/ARM64/diags.s
+++ b/test/MC/ARM64/diags.s
@@ -74,6 +74,18 @@ foo:
 ; CHECK-ERRORS:                   ^
 
 
+; Check that register offset addressing modes only accept 32-bit offset
+; registers when using uxtw/sxtw extends. Everything else requires a 64-bit
+; register.
+  str    d1, [x3, w3, sxtx #3]
+  ldr    s1, [x3, d3, sxtx #2]
+
+; CHECK-ERRORS: 32-bit general purpose offset register requires sxtw or uxtw extend
+; CHECK-ERRORS:   str    d1, [x3, w3, sxtx #3]
+; CHECK-ERRORS:                       ^
+; CHECK-ERRORS: error: 64-bit general purpose offset register expected
+; CHECK-ERRORS:   ldr    s1, [x3, d3, sxtx #2]
+; CHECK-ERRORS:                   ^
 
 ; Shift immediates range checking.
   sqrshrn b4, h9, #10